Cross Reference: /illumos-gate/usr/src/uts/common/io/chxge/com/tp.c

Lines Matching refs:ap
173 static void tp_init(adapter_t *ap, const struct tp_params *p,
176 	if (t1_is_asic(ap)) {
186 		t1_write_reg_4(ap, A_TP_IN_CONFIG, val);
187 		t1_write_reg_4(ap, A_TP_OUT_CONFIG, F_TP_OUT_CSPI_CPL |
191 		t1_write_reg_4(ap, A_TP_GLOBAL_CONFIG, V_IP_TTL(64) |
199                 if (is_T2(ap) && ap->params.nports > 1) {
202                         t1_write_reg_4(ap, A_TP_TX_DROP_CONFIG,
209 		t1_write_reg_4(ap, A_TP_GLOBAL_RX_CREDITS, 0xffffffff);
215 		if (ap->params.nports == 1)
217 		t1_write_reg_4(ap, A_TP_TCP_OPTIONS, val);
218 		t1_write_reg_4(ap, A_TP_DACK_CONFIG, V_DACK_MSS_SELECTOR(1) |
220 		t1_write_reg_4(ap, A_TP_BACKOFF0, 0x3020100);
221 		t1_write_reg_4(ap, A_TP_BACKOFF1, 0x7060504);
222 		t1_write_reg_4(ap, A_TP_BACKOFF2, 0xb0a0908);
223 		t1_write_reg_4(ap, A_TP_BACKOFF3, 0xf0e0d0c);
229 		if (ap->params.nports == 1)
230 			t1_write_reg_4(ap, A_TP_PARA_REG0, 0xd1269324);
232 			t1_write_reg_4(ap, A_TP_PARA_REG0, 0xd6269324);
233 		t1_write_reg_4(ap, A_TP_SYNC_TIME_HI, 0);
234 		t1_write_reg_4(ap, A_TP_SYNC_TIME_LO, 0);
235 		t1_write_reg_4(ap, A_TP_INT_ENABLE, 0);
236 		t1_write_reg_4(ap, A_TP_CM_FC_MODE, 0);   /* Enable CM cache */
237 		t1_write_reg_4(ap, A_TP_PC_CONGESTION_CNTL, 0x6186);
253 		if (ap->params.nports > 1) {
256 		if (is_10G(ap))               /* adjust for 10G */
261 		t1_write_reg_4(ap, A_TP_TIMER_SEPARATOR, val & ~1);
263 		t1_write_reg_4(ap, A_TP_TIMER_RESOLUTION, 0xF0011);
264 		tp_set_tcp_time_params(ap, tp_clk);
267 		if (is_T2(ap)) {
268 			val = t1_read_reg_4(ap, A_TP_PC_CONFIG);
270 			t1_write_reg_4(ap, A_TP_PC_CONFIG, val);
275 		t1_write_reg_4(ap, A_TP_TIMER_RESOLUTION, 0xD000A);