Lines Matching defs:adapter
36 adapter_t *adapter;
52 static void tp_pm_configure(adapter_t *adapter, struct tp_params *p)
64 t1_write_reg_4(adapter, A_TP_PM_SIZE, p->pm_size);
65 t1_write_reg_4(adapter, A_TP_PM_RX_BASE, p->pm_rx_base);
66 t1_write_reg_4(adapter, A_TP_PM_TX_BASE, p->pm_tx_base);
67 t1_write_reg_4(adapter, A_TP_PM_DEFRAG_BASE, p->pm_size);
68 t1_write_reg_4(adapter, A_TP_PM_RX_PG_SIZE, p->pm_rx_pg_size);
69 t1_write_reg_4(adapter, A_TP_PM_RX_MAX_PGS, p->pm_rx_num_pgs);
70 t1_write_reg_4(adapter, A_TP_PM_TX_PG_SIZE, p->pm_tx_pg_size);
71 t1_write_reg_4(adapter, A_TP_PM_TX_MAX_PGS, p->pm_tx_num_pgs);
74 static void tp_cm_configure(adapter_t *adapter, u32 cm_size)
79 t1_write_reg_4(adapter, A_TP_CM_SIZE, cm_size);
80 t1_write_reg_4(adapter, A_TP_CM_MM_BASE, mm_base);
81 t1_write_reg_4(adapter, A_TP_CM_TIMER_BASE, (cm_size >> 2) * 3);
82 t1_write_reg_4(adapter, A_TP_CM_MM_P_FLST_BASE,
84 t1_write_reg_4(adapter, A_TP_CM_MM_TX_FLST_BASE,
86 t1_write_reg_4(adapter, A_TP_CM_MM_RX_FLST_BASE,
88 t1_write_reg_4(adapter, A_TP_CM_MM_MAX_P, 0x40000);
105 static void tp_set_tcp_time_params(adapter_t *adapter, unsigned int tp_clk)
107 u32 tps = t1_tp_ticks_per_sec(adapter, tp_clk);
111 t1_write_reg_4(adapter, A_TP_2MSL, (1 SECONDS)/2);
112 t1_write_reg_4(adapter, A_TP_RXT_MIN, (1 SECONDS)/4);
113 t1_write_reg_4(adapter, A_TP_RXT_MAX, 64 SECONDS);
114 t1_write_reg_4(adapter, A_TP_PERS_MIN, (1 SECONDS)/2);
115 t1_write_reg_4(adapter, A_TP_PERS_MAX, 64 SECONDS);
116 t1_write_reg_4(adapter, A_TP_KEEP_IDLE, 7200 SECONDS);
117 t1_write_reg_4(adapter, A_TP_KEEP_INTVL, 75 SECONDS);
118 t1_write_reg_4(adapter, A_TP_INIT_SRTT, 3 SECONDS);
119 t1_write_reg_4(adapter, A_TP_FINWAIT2_TIME, 60 SECONDS);
120 t1_write_reg_4(adapter, A_TP_FAST_FINWAIT2_TIME, 3 SECONDS);
124 tp_scnt = t1_read_reg_4(adapter, A_TP_SHIFT_CNT);
127 t1_write_reg_4(adapter, A_TP_SHIFT_CNT, tp_scnt);
130 t1_write_reg_4(adapter, A_TP_DACK_TIME,
131 tp_delayed_ack_ticks(adapter, tp_clk) / 5);
141 val = t1_read_reg_4(tp->adapter, A_TP_PARA_REG3);
143 if (tp->adapter->params.nports > 1)
147 u32 v = t1_is_T1B(tp->adapter) ? 0 : V_MAX_RX_SIZE(size);
150 t1_write_reg_4(tp->adapter, A_TP_PARA_REG2,
157 t1_write_reg_4(tp->adapter, A_TP_PARA_REG3, val);
286 struct petp * __devinit t1_tp_create(adapter_t *adapter, struct tp_params *p)
292 tp->adapter = adapter;
304 if (adapter->params.nports == 1)
319 u32 tp_intr = t1_read_reg_4(tp->adapter, A_PL_ENABLE);
322 if (!t1_is_asic(tp->adapter)) {
324 t1_write_reg_4(tp->adapter, FPGA_TP_ADDR_INTERRUPT_ENABLE,
326 t1_write_reg_4(tp->adapter, A_PL_ENABLE,
332 t1_write_reg_4(tp->adapter, A_TP_INT_ENABLE, 0);
333 t1_write_reg_4(tp->adapter, A_PL_ENABLE,
340 u32 tp_intr = t1_read_reg_4(tp->adapter, A_PL_ENABLE);
343 if (!t1_is_asic(tp->adapter)) {
345 t1_write_reg_4(tp->adapter, FPGA_TP_ADDR_INTERRUPT_ENABLE, 0);
346 t1_write_reg_4(tp->adapter, A_PL_ENABLE,
351 t1_write_reg_4(tp->adapter, A_TP_INT_ENABLE, 0);
352 t1_write_reg_4(tp->adapter, A_PL_ENABLE,
360 if (!t1_is_asic(tp->adapter)) {
361 t1_write_reg_4(tp->adapter, FPGA_TP_ADDR_INTERRUPT_CAUSE,
363 t1_write_reg_4(tp->adapter, A_PL_CAUSE, FPGA_PCIX_INTERRUPT_TP);
367 t1_write_reg_4(tp->adapter, A_TP_INT_CAUSE, 0xffffffff);
368 t1_write_reg_4(tp->adapter, A_PL_CAUSE, F_PL_INTR_TP);
377 if (!t1_is_asic(tp->adapter))
381 cause = t1_read_reg_4(tp->adapter, A_TP_INT_CAUSE);
382 t1_write_reg_4(tp->adapter, A_TP_INT_CAUSE, cause);
388 u32 val = t1_read_reg_4(tp->adapter, A_TP_GLOBAL_CONFIG);
394 t1_write_reg_4(tp->adapter, A_TP_GLOBAL_CONFIG, val);
419 adapter_t *adapter = tp->adapter;
421 tp_init(adapter, p, tp_clk);
424 tp_pm_configure(adapter, p);
425 tp_cm_configure(adapter, p->cm_size);
427 t1_write_reg_4(adapter, A_TP_RESET, F_CM_MEMMGR_INIT);
428 busy = t1_wait_op_done(adapter, A_TP_RESET, F_CM_MEMMGR_INIT,
433 t1_write_reg_4(adapter, A_TP_RESET, F_TP_RESET);
436 adapter_name(adapter));