Lines Matching defs:OFFSET
46 #define OFFSET(REG_ADDR) (REG_ADDR << 2)
97 (void) t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
103 (void) t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
558 (void) t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \
559 (void) t1_tpi_read((mac)->adapter, OFFSET(((name)+1)), &val1); \
560 (void) t1_tpi_read((mac)->adapter, OFFSET(((name)+2)), &val2); \
744 (void) t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000);
745 (void) t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000);
746 (void) t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800);
747 (void) t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001); /* PL4IO Enable */
748 (void) t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800);
749 (void) t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800);
750 (void) t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800);
751 (void) t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800);
752 (void) t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800);
753 (void) t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800);
754 (void) t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800);
755 (void) t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800);
756 (void) t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800);
757 (void) t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800);
758 (void) t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800);
759 (void) t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800);
760 (void) t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800);
761 (void) t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800);
762 (void) t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800);
763 (void) t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800);
764 (void) t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00);
765 (void) t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202); /* PL4IO Calendar Repetitions */
767 (void) t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080); /* EFLX Enable */
768 (void) t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000); /* EFLX Channel Deprovision */
769 (void) t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000); /* EFLX Low Limit */
770 (void) t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040); /* EFLX High Limit */
771 (void) t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc); /* EFLX Almost Full */
772 (void) t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199); /* EFLX Almost Empty */
773 (void) t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240); /* EFLX Cut Through Threshold */
774 (void) t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000); /* EFLX Indirect Register Update */
775 (void) t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001); /* EFLX Channel Provision */
776 (void) t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff); /* EFLX Undocumented */
777 (void) t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff); /* EFLX Undocumented */
778 (void) t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff); /* EFLX enable overflow interrupt The other bit are undocumented */
779 (void) t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff); /* EFLX Undocumented */
781 (void) t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000); /* IFLX Configuration - enable */
782 (void) t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000); /* IFLX Channel Deprovision */
783 (void) t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000); /* IFLX Low Limit */
784 (void) t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100); /* IFLX High Limit */
785 (void) t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00); /* IFLX Almost Full Limit */
786 (void) t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599); /* IFLX Almost Empty Limit */
787 (void) t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000); /* IFLX Indirect Register Update */
788 (void) t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001); /* IFLX Channel Provision */
789 (void) t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff); /* IFLX Undocumented */
790 (void) t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff); /* IFLX Undocumented */
791 (void) t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff); /* IFLX Enable overflow interrupt. The other bit are undocumented */
793 (void) t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe); /* PL4MOS Undocumented */
794 (void) t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff); /* PL4MOS Undocumented */
795 (void) t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008); /* PL4MOS Starving Burst Size */
796 (void) t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008); /* PL4MOS Hungry Burst Size */
797 (void) t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008); /* PL4MOS Transfer Size */
798 (void) t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005); /* PL4MOS Disable */
800 (void) t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103); /* PL4ODP Training Repeat and SOP rule */
801 (void) t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000); /* PL4ODP MAX_T setting */
803 (void) t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087); /* PL4IDU Enable data forward, port state machine. Set ALLOW_NON_ZERO_OLB */
804 (void) t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f); /* PL4IDU Enable Dip4 check error interrupts */
806 (void) t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32); /* # TXXG Config */
808 (void) t1_tpi_write(adapter, OFFSET(0x304d), 0x8000);
809 (void) t1_tpi_write(adapter, OFFSET(0x2040), 0x059c); /* # RXXG Config */
810 (void) t1_tpi_write(adapter, OFFSET(0x2049), 0x0001); /* # RXXG Cut Through */
811 (void) t1_tpi_write(adapter, OFFSET(0x2070), 0x0000); /* # Disable promiscuous mode */
815 (void) t1_tpi_write(adapter, OFFSET(0x206e), 0x0000); /* # Disable Match Enable bit */
816 (void) t1_tpi_write(adapter, OFFSET(0x204a), 0xffff); /* # low addr */
817 (void) t1_tpi_write(adapter, OFFSET(0x204b), 0xffff); /* # mid addr */
818 (void) t1_tpi_write(adapter, OFFSET(0x204c), 0xffff); /* # high addr */
819 (void) t1_tpi_write(adapter, OFFSET(0x206e), 0x0009); /* # Enable Match Enable bit */
821 (void) t1_tpi_write(adapter, OFFSET(0x0003), 0x0000); /* # NO SOP/ PAD_EN setup */
822 (void) t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0); /* # RXEQB disabled */
823 (void) t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f); /* # No Preemphasis */
896 (void) t1_tpi_read(adapter, OFFSET(SUNI1x10GEXP_REG_DEVICE_STATUS), &val);