Lines Matching defs:adapter
37 adapter_t *adapter;
48 u32 en = t1_read_reg_4(mc3->adapter, A_PL_ENABLE);
50 if (t1_is_asic(mc3->adapter)) {
51 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, MC3_INTR_MASK);
52 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, en | F_PL_INTR_MC3);
55 t1_write_reg_4(mc3->adapter, FPGA_MC3_REG_INTRENABLE,
57 t1_write_reg_4(mc3->adapter, A_PL_ENABLE,
65 u32 pl_intr = t1_read_reg_4(mc3->adapter, A_PL_ENABLE);
67 if (t1_is_asic(mc3->adapter)) {
68 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, 0);
69 t1_write_reg_4(mc3->adapter, A_PL_ENABLE,
73 t1_write_reg_4(mc3->adapter, FPGA_MC3_REG_INTRENABLE, 0);
74 t1_write_reg_4(mc3->adapter, A_PL_ENABLE,
82 if (t1_is_asic(mc3->adapter)) {
83 if (t1_is_T1B(mc3->adapter)) {
90 old_en = t1_read_reg_4(mc3->adapter, A_MC3_INT_ENABLE);
91 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE,
93 t1_write_reg_4(mc3->adapter, A_MC3_INT_ENABLE, old_en);
95 t1_write_reg_4(mc3->adapter, A_MC3_INT_CAUSE,
98 t1_write_reg_4(mc3->adapter, A_PL_CAUSE, F_PL_INTR_MC3);
101 t1_write_reg_4(mc3->adapter, FPGA_MC3_REG_INTRCAUSE,
103 t1_write_reg_4(mc3->adapter, A_PL_CAUSE,
111 adapter_t *adapter = mc3->adapter;
116 if (!t1_is_asic(adapter))
119 cause = t1_read_reg_4(adapter, cause_reg);
125 adapter_name(adapter),
126 G_MC3_CE_ADDR(t1_read_reg_4(adapter, A_MC3_CE_ADDR)),
127 t1_read_reg_4(adapter, A_MC3_CE_DATA0),
128 t1_read_reg_4(adapter, A_MC3_CE_DATA1),
129 t1_read_reg_4(adapter, A_MC3_CE_DATA2),
130 t1_read_reg_4(adapter, A_MC3_CE_DATA3),
131 t1_read_reg_4(adapter, A_MC3_CE_DATA4));
138 adapter_name(adapter),
139 G_MC3_UE_ADDR(t1_read_reg_4(adapter, A_MC3_UE_ADDR)),
140 t1_read_reg_4(adapter, A_MC3_UE_DATA0),
141 t1_read_reg_4(adapter, A_MC3_UE_DATA1),
142 t1_read_reg_4(adapter, A_MC3_UE_DATA2),
143 t1_read_reg_4(adapter, A_MC3_UE_DATA3),
144 t1_read_reg_4(adapter, A_MC3_UE_DATA4));
149 CH_ALERT("%s: MC3 parity error 0x%x\n", adapter_name(adapter),
155 CH_ALERT("%s: MC3 address error\n", adapter_name(adapter));
159 t1_fatal_err(adapter);
161 if (t1_is_T1B(adapter)) {
166 t1_write_reg_4(adapter, A_MC3_INT_ENABLE, cause);
168 t1_write_reg_4(adapter, A_MC3_INT_ENABLE, MC3_INTR_MASK);
170 t1_write_reg_4(adapter, cause_reg, cause);
175 #define is_MC3A(adapter) (!t1_is_T1B(adapter))
182 static int wrreg_wait(adapter_t *adapter, unsigned int addr, u32 val)
184 t1_write_reg_4(adapter, addr, val);
185 val = t1_read_reg_4(adapter, addr); /* flush */
186 if (!(t1_read_reg_4(adapter, addr) & F_BUSY))
189 adapter_name(adapter), addr);
199 adapter_t *adapter = mc3->adapter;
202 val = t1_read_reg_4(adapter, A_MC3_CFG);
203 width = is_MC3A(adapter) ? G_MC3_WIDTH(val) : 0;
204 fast_asic = t1_is_asic(adapter) && !(val & F_MC3_SLOW);
227 t1_write_reg_4(adapter, A_MC3_CFG, val);
229 val = t1_read_reg_4(adapter, A_MC3_CFG);
230 t1_write_reg_4(adapter, A_MC3_CFG, val | F_CLK_ENABLE);
231 val = t1_read_reg_4(adapter, A_MC3_CFG); /* flush */
234 val = t1_read_reg_4(adapter, A_MC3_STROBE);
235 if (is_MC3A(adapter)) {
236 t1_write_reg_4(adapter, A_MC3_STROBE,
243 t1_write_reg_4(adapter, A_MC3_STROBE,
250 val = t1_read_reg_4(adapter, A_MC3_STROBE);
254 adapter_name(adapter));
261 if (wrreg_wait(adapter, A_MC3_PRECHARG, 0))
265 if (wrreg_wait(adapter, A_MC3_EXT_MODE, fast_asic ? 0 : 1))
269 if (wrreg_wait(adapter, A_MC3_MODE, fast_asic ? 0x161 : 0x21))
273 if (wrreg_wait(adapter, A_MC3_PRECHARG, 0))
277 val = t1_read_reg_4(adapter, A_MC3_REFRESH);
278 if (wrreg_wait(adapter, A_MC3_REFRESH, val & ~F_REFRESH_ENABLE))
282 if (wrreg_wait(adapter, A_MC3_REFRESH, val & ~F_REFRESH_ENABLE))
286 if (wrreg_wait(adapter, A_MC3_MODE, fast_asic ? 0x61 : 0x21))
295 t1_write_reg_4(adapter, A_MC3_REFRESH,
297 (void) t1_read_reg_4(adapter, A_MC3_REFRESH); /* flush */
299 t1_write_reg_4(adapter, A_MC3_ECC_CNTL,
303 t1_write_reg_4(adapter, A_MC3_BIST_ADDR_BEG, 0);
304 t1_write_reg_4(adapter, A_MC3_BIST_ADDR_END, (mc3->size << width) - 1);
305 t1_write_reg_4(adapter, A_MC3_BIST_DATA, 0);
306 t1_write_reg_4(adapter, A_MC3_BIST_OP, V_OP(1) | 0x1f0);
307 (void) t1_read_reg_4(adapter, A_MC3_BIST_OP); /* flush */
312 val = t1_read_reg_4(adapter, A_MC3_BIST_OP);
315 CH_ERR("%s: MC3 BIST timed out\n", adapter_name(adapter));
320 val = t1_read_reg_4(adapter, A_MC3_CFG);
321 t1_write_reg_4(adapter, A_MC3_CFG, val | F_READY);
328 static unsigned int __devinit mc3_calc_size(const adapter_t *adapter, u32 cfg)
334 unsigned int capacity_in_MB = is_MC3A(adapter) ?
341 struct pemc3 * __devinit t1_mc3_create(adapter_t *adapter)
346 mc3->adapter = adapter;
347 mc3->size = mc3_calc_size(adapter,
348 t1_read_reg_4(adapter, A_MC3_CFG));