Lines Matching defs:adapter
33 adapter_t *adapter;
49 static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr,
54 t1_write_reg_4(adapter, A_ESPI_CMD_ADDR, V_WRITE_DATA(wr_data) |
59 t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
61 busy = t1_wait_op_done(adapter, A_ESPI_GOSTAT, F_ESPI_CMD_BUSY, 0,
65 CH_ERR("%s: TRICN write timed out\n", adapter_name(adapter));
71 static int tricn_read(adapter_t *adapter, int bundle_addr, int module_addr,
77 t1_write_reg_4(adapter, A_ESPI_CMD_ADDR,
82 t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
85 status = t1_read_reg_4(adapter, A_ESPI_GOSTAT);
90 CH_ERR("%s: TRICN read timed out\n", adapter_name(adapter));
97 static int tricn_init(adapter_t *adapter)
101 if (!(t1_read_reg_4(adapter, A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) {
102 CH_ERR("%s: ESPI clock not ready\n", adapter_name(adapter));
106 t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST);
109 (void) tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81);
110 (void) tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81);
111 (void) tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81);
113 for (i=1; i<= 8; i++) (void) tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1);
114 for (i=1; i<= 2; i++) (void) tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1);
115 for (i=1; i<= 3; i++) (void) tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
116 (void) tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1);
117 (void) tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1);
118 (void) tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1);
119 (void) tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80);
120 (void) tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1);
122 t1_write_reg_4(adapter, A_ESPI_RX_RESET, F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST);
129 u32 enable, pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE);
138 enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK;
139 t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, enable);
140 t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr | F_PL_INTR_ESPI);
145 (void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT);
146 t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, 0xffffffff);
147 t1_write_reg_4(espi->adapter, A_PL_CAUSE, F_PL_INTR_ESPI);
152 u32 pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE);
154 t1_write_reg_4(espi->adapter, A_ESPI_INTR_ENABLE, 0);
155 t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr & ~F_PL_INTR_ESPI);
160 u32 status = t1_read_reg_4(espi->adapter, A_ESPI_INTR_STATUS);
174 (void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT);
181 if (status && t1_is_T1B(espi->adapter))
183 t1_write_reg_4(espi->adapter, A_ESPI_INTR_STATUS, status);
192 static void espi_setup_for_pm3393(adapter_t *adapter)
194 u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
196 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
197 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f4);
198 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
199 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN3, 0x1f4);
200 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x100);
201 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, wmark);
202 t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 3);
203 t1_write_reg_4(adapter, A_ESPI_TRAIN, 0x08000008);
204 t1_write_reg_4(adapter, A_PORT_CONFIG,
208 static void espi_setup_for_vsc7321(adapter_t *adapter)
211 u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
213 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
214 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f4);
215 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
216 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN3, 0x1f4);
217 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x100);
218 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, wmark);
219 t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 3);
220 t1_write_reg_4(adapter, A_PORT_CONFIG,
223 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN0, 0x1f4);
224 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN1, 0x1f401f4);
225 t1_write_reg_4(adapter, A_ESPI_SCH_TOKEN2, 0x1f4);
226 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK, 0xa00);
227 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK, 0x1ff);
228 t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 1);
229 t1_write_reg_4(adapter, A_PORT_CONFIG,
232 t1_write_reg_4(adapter, A_ESPI_TRAIN, 0x08000008);
238 static void espi_setup_for_ixf1010(adapter_t *adapter, int nports)
240 t1_write_reg_4(adapter, A_ESPI_CALENDAR_LENGTH, 1);
242 if (is_T2(adapter)) {
243 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
245 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
248 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
250 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
254 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK,
256 t1_write_reg_4(adapter, A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK,
259 t1_write_reg_4(adapter, A_PORT_CONFIG,
266 adapter_t *adapter = espi->adapter;
269 t1_write_reg_4(adapter, A_ESPI_TRAIN, 0);
271 if (is_T2(adapter)) {
272 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
275 t1_write_reg_4(adapter, A_ESPI_MAXBURST1_MAXBURST2,
278 t1_write_reg_4(adapter, A_ESPI_MAXBURST1_MAXBURST2, 0x800100);
281 espi_setup_for_pm3393(adapter);
283 espi_setup_for_vsc7321(adapter);
286 espi_setup_for_ixf1010(adapter, nports);
290 t1_write_reg_4(adapter, A_ESPI_FIFO_STATUS_ENABLE,
293 if (is_T2(adapter)) {
294 (void) tricn_init(adapter);
299 espi->misc_ctrl = t1_read_reg_4(adapter, A_ESPI_MISC_CONTROL);
302 if (adapter->params.nports == 1)
304 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
313 if (is_T2(espi->adapter)) {
319 struct peespi *t1_espi_create(adapter_t *adapter)
324 espi->adapter = adapter;
328 void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
330 struct peespi *espi = adapter->espi;
332 if (!is_T2(adapter))
337 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
341 u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
343 struct peespi *espi = adapter->espi;
346 if (!is_T2(adapter)) return 0;
355 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
357 sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);
358 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
362 sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);
373 t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait)
375 struct peespi *espi = adapter->espi;
376 u8 i, nport = (u8)adapter->params.nports;
386 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);
390 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL,
393 *valp = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3);
396 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, espi->misc_ctrl);