Lines Matching defs:MISC_REG_SPIO
5992 #define MISC_REG_SPIO 0xa4fcUL //ACCESS:RW DataWidth:0x20 Description: SPIO. [31-24] FLOAT When any of these bits is written as a '1'; the corresponding SPIO bit will turn off it's drivers and become an input. This is the reset state of all SPIO pins. The read value of these bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits is written as a '1'; the corresponding SPIO bit will drive low. The read value of these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of these bits is written as a '1'; the corresponding SPIO bit will drive high (if it has that capability). The read value of these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. (reset value 0). [7-0] VALUE RO; These bits indicate the read value of each of the eight SPIO pins. This is the result value of the pin; not the drive value. Writing these bits will have not effect. Each 8 bits field is divided as follows: [0] VAUX Enable; when pulsed low; enables supply from VAUX. (This is an output pin only; the FLOAT field is not applicable for this pin); [1] VAUX Disable; when pulsed low; disables supply form VAUX. (This is an output pin only; FLOAT field is not applicable for this pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to select VAUX supply. (This is an output pin only; it is not controlled by the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT field is not applicable for this pin; only the VALUE fields is relevant - it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6] Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP device ID select; read by UMP firmware. Global register.