Lines Matching defs:MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0

5430 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0                                                                                  0xa10cUL //ACCESS:RW  DataWidth:0x20  Description: first 32b for enabling the output for function 1 output0. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw interrupt;