Lines Matching defs:MISC_REG_AEU_CLR_LATCH_SIGNAL

5930 #define MISC_REG_AEU_CLR_LATCH_SIGNAL                                                                                      0xa45cUL //ACCESS:W  DataWidth:0xe  Description: write to this register results with the clear of the latched signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP latch; one in d5 clears GRC Latched timeout attention; one in d6 clears GRC Latched reserved access attention; one in d7 clears Latched rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears pxp_misc_exp_rom_attn0;  one in d13 clears pxp_misc_exp_rom_attn1;  read from this register return zero