Lines Matching defs:HC_REG_TRAILING_EDGE_1
4851 #define HC_REG_TRAILING_EDGE_1 0x10804cUL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: port 1 attn bit condition monitoring; each bit that is set will lock a change fron 1 to 0 in the corresponding attention signals that comes from the AEU