Lines Matching defs:HC_REG_LEADING_EDGE_1
4850 #define HC_REG_LEADING_EDGE_1 0x108048UL //ACCESS:RW DataWidth:0x10 SPLIT:4 Description: port 1 attn bit condition monitoring; each bit that is set will lock a change fron 0 to 1 in the corresponding attention signals that comes from the AEU