Lines Matching defs:HC_REG_INT_MASK
4971 #define HC_REG_INT_MASK 0x108108UL //ACCESS:RW DataWidth:0x11 SPLIT:4 Description: status block interrupt mask; one in each bit means unmask; zerow in each bit means mask; bit 0 - default SB; bit 1 - SB_0; bit 2 - SB_1 to bit 16- SB_15; addr 0 - port 0; addr 1 - port 1