Lines Matching refs:cb
65 #define MSLEEP(cb, ms) elink_cb_udelay(cb, 1000*ms)
66 #define USLEEP(cb, us) elink_cb_udelay(cb, us)
67 #define REG_RD(cb, reg) elink_cb_reg_read(cb, reg)
68 #define REG_WR(cb, reg, val) elink_cb_reg_write(cb, reg, val)
69 #define EMAC_RD(cb, reg) REG_RD(cb, emac_base + reg)
70 #define EMAC_WR(cb, reg, val) REG_WR(cb, emac_base + reg, val)
71 #define REG_WR_DMAE(cb, offset, wb_data, len) \
72 elink_cb_reg_wb_write(cb, offset, wb_data, len)
73 #define REG_RD_DMAE(cb, offset, wb_data, len) \
74 elink_cb_reg_wb_read(cb, offset, wb_data, len)
75 #define PATH_ID(cb) elink_cb_path_id(cb)
161 #define SHMEM2_RD(cb, shmem2_base, _field) \
162 REG_RD(cb, shmem2_base + \
166 #define SHMEM2_HAS(cb, shmem2_base, field) (shmem2_base && \
167 (SHMEM2_RD(cb, shmem2_base, size) > \
345 static u32 elink_bits_en(struct elink_dev *cb, u32 reg, u32 bits)
347 u32 val = REG_RD(cb, reg);
350 REG_WR(cb, reg, val);
354 static u32 elink_bits_dis(struct elink_dev *cb, u32 reg, u32 bits)
356 u32 val = REG_RD(cb, reg);
359 REG_WR(cb, reg, val);
377 struct elink_dev *cb = params->cb;
380 REG_RD(cb, params->lfa_base +
387 ELINK_DEBUG_P0(cb, "No LFA due to DCC flap after clp exit\n");
388 REG_WR(cb, params->lfa_base +
395 link_status = REG_RD(cb, params->shmem_base +
424 saved_val = REG_RD(cb, params->lfa_base +
428 ELINK_DEBUG_P2(cb, "Duplex mismatch %x vs. %x\n",
433 saved_val = REG_RD(cb, params->lfa_base +
437 ELINK_DEBUG_P2(cb, "Flow control mismatch %x vs. %x\n",
442 saved_val = REG_RD(cb, params->lfa_base +
446 ELINK_DEBUG_P2(cb, "Link speed mismatch %x vs. %x\n",
452 cur_speed_cap_mask = REG_RD(cb, params->lfa_base +
457 ELINK_DEBUG_P2(cb, "Speed Cap mismatch %x vs. %x\n",
465 REG_RD(cb, params->lfa_base +
470 ELINK_DEBUG_P2(cb, "Flow Ctrl AN mismatch %x vs. %x\n",
475 eee_status = REG_RD(cb, params->shmem2_base +
483 ELINK_DEBUG_P2(cb, "EEE mismatch %x vs. %x\n", params->eee_mode,
496 static void elink_get_epio(struct elink_dev *cb, u32 epio_pin, u32 *en)
502 ELINK_DEBUG_P1(cb, "Invalid EPIO pin %d to get\n", epio_pin);
508 gp_oenable = REG_RD(cb, MCP_REG_MCPR_GP_OENABLE);
509 REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
511 *en = (REG_RD(cb, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
513 static void elink_set_epio(struct elink_dev *cb, u32 epio_pin, u32 en)
519 ELINK_DEBUG_P1(cb, "Invalid EPIO pin %d to set\n", epio_pin);
522 ELINK_DEBUG_P2(cb, "Setting EPIO pin %d to %d\n", epio_pin, en);
525 gp_output = REG_RD(cb, MCP_REG_MCPR_GP_OUTPUTS);
531 REG_WR(cb, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
534 gp_oenable = REG_RD(cb, MCP_REG_MCPR_GP_OENABLE);
535 REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
538 static void elink_set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val)
543 elink_set_epio(cb, pin_cfg - PIN_CFG_EPIO0, val);
547 ELINK_SET_GPIO(cb, gpio_num, (u8)val, gpio_port);
551 static u32 elink_get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val)
556 elink_get_epio(cb, pin_cfg - PIN_CFG_EPIO0, val);
560 *val = ELINK_GET_GPIO(cb, gpio_num, gpio_port);
573 struct elink_dev *cb = params->cb;
575 ELINK_DEBUG_P0(cb, "ETS E2E3 disabled configuration\n");
584 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
593 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
595 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
599 REG_WR(cb, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
603 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
604 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
605 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
607 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
608 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
609 REG_WR(cb, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
611 REG_WR(cb, PBF_REG_ETS_ENABLED, 0);
615 REG_WR(cb, PBF_REG_COS0_WEIGHT, 0x2710);
616 REG_WR(cb, PBF_REG_COS1_WEIGHT, 0x2710);
618 REG_WR(cb, PBF_REG_COS0_UPPER_BOUND, 0x989680);
619 REG_WR(cb, PBF_REG_COS1_UPPER_BOUND, 0x989680);
621 REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
664 struct elink_dev *cb = params->cb;
669 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
671 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
673 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
675 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
677 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
679 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
683 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
685 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
687 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
702 struct elink_dev *cb = params->cb;
711 REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
712 REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
714 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
715 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
720 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
727 REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
728 REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
731 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
733 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
744 REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
746 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
748 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
757 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
759 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
761 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
763 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
765 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
767 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
770 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
771 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
772 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
786 struct elink_dev *cb = params->cb;
805 REG_WR(cb, base_upper_bound + (i << 2), credit_upper_bound);
818 struct elink_dev *cb = params->cb;
831 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
834 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
839 REG_WR(cb, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
842 REG_WR(cb, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
844 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
848 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
851 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
865 REG_WR(cb, base_weight + (0x4 * i), 0);
877 struct elink_dev *cb = params->cb;
880 ELINK_DEBUG_P0(cb,
900 struct elink_dev *cb = params->cb;
908 ELINK_DEBUG_P0(cb, "elink_ets_disabled - chip not supported\n");
925 struct elink_dev *cb = params->cb;
932 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
935 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
938 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
942 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
954 static elink_status_t elink_ets_e3b0_set_cos_bw(struct elink_dev *cb,
1015 REG_WR(cb, nig_reg_adress_crd_weight, cos_bw_nig);
1017 REG_WR(cb, pbf_reg_adress_crd_weight, cos_bw_pbf);
1031 struct elink_dev *cb = params->cb;
1041 ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config BW"
1057 ELINK_DEBUG_P0(cb,
1061 ELINK_DEBUG_P0(cb,
1091 struct elink_dev *cb = params->cb;
1097 ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
1103 ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
1172 struct elink_dev *cb = params->cb;
1189 ELINK_DEBUG_P0(cb,
1203 ELINK_DEBUG_P0(cb,
1232 ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_set_pri_cli_reg not all "
1239 REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1242 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1248 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1250 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1253 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1266 struct elink_dev *cb = params->cb;
1280 ELINK_DEBUG_P0(cb,
1286 ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config the number of COS "
1298 ELINK_DEBUG_P0(cb,
1317 cb, cos_entry, min_w_val_nig, min_w_val_pbf,
1332 ELINK_DEBUG_P0(cb,
1337 ELINK_DEBUG_P0(cb,
1348 ELINK_DEBUG_P0(cb,
1359 ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config SP failed\n");
1367 struct elink_dev *cb = params->cb;
1368 ELINK_DEBUG_P0(cb, "ETS enabled BW limit configuration\n");
1373 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1380 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1382 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1384 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1388 REG_WR(cb, PBF_REG_ETS_ENABLED, 1);
1391 REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1399 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1402 REG_WR(cb, PBF_REG_COS0_UPPER_BOUND,
1404 REG_WR(cb, PBF_REG_COS1_UPPER_BOUND,
1412 struct elink_dev *cb = params->cb;
1417 ELINK_DEBUG_P0(cb, "ETS enabled BW limit configuration\n");
1422 ELINK_DEBUG_P0(cb, "Total BW can't be zero\n");
1433 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1434 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1436 REG_WR(cb, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1437 REG_WR(cb, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1443 struct elink_dev *cb = params->cb;
1446 ELINK_DEBUG_P0(cb, "ETS enabled strict configuration\n");
1454 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1458 REG_WR(cb, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1460 REG_WR(cb, PBF_REG_ETS_ENABLED, 0);
1462 REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1465 REG_WR(cb, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1475 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1490 struct elink_dev *cb = params->cb;
1521 REG_WR(cb, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1522 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1523 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1529 REG_WR(cb, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1530 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1531 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1535 REG_WR(cb, xmac_base + XMAC_REG_CTRL_SA_LO,
1540 REG_WR(cb, xmac_base + XMAC_REG_CTRL_SA_HI,
1544 USLEEP(cb, 30);
1556 struct elink_dev *cb = params->cb;
1561 ELINK_DEBUG_P0(cb, "pfc statistic read from EMAC\n");
1564 val_xoff = REG_RD(cb, emac_base +
1567 val_xon = REG_RD(cb, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1573 val_xoff = REG_RD(cb, emac_base +
1576 val_xon = REG_RD(cb, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1588 struct elink_dev *cb = params->cb;
1590 ELINK_DEBUG_P0(cb, "pfc statistic\n");
1596 ELINK_DEBUG_P0(cb, "About to read PFC stats from EMAC\n");
1606 static void elink_set_mdio_clk(struct elink_dev *cb, u32 chip_id,
1614 cur_mode = REG_RD(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1630 ELINK_DEBUG_P2(cb, "Changing emac_mode from 0x%x to 0x%x\n",
1632 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1633 USLEEP(cb, 40);
1637 static u8 elink_is_4_port_mode(struct elink_dev *cb)
1641 port4mode_ovwr_val = REG_RD(cb, MISC_REG_PORT4MODE_EN_OVWR);
1647 return (u8)REG_RD(cb, MISC_REG_PORT4MODE_EN);
1652 static void elink_set_mdio_emac_per_phy(struct elink_dev *cb,
1660 elink_set_mdio_clk(cb, params->chip_id,
1668 struct elink_dev *cb = params->cb;
1674 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1676 USLEEP(cb, 5);
1677 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1682 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE);
1683 EMAC_WR(cb, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1687 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE);
1688 ELINK_DEBUG_P1(cb, "EMAC reset reg is %u\n", val);
1690 ELINK_DEBUG_P0(cb, "EMAC timeout!\n");
1696 elink_set_mdio_emac_per_phy(cb, params);
1700 EMAC_WR(cb, EMAC_REG_EMAC_MAC_MATCH, val);
1706 EMAC_WR(cb, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1714 struct elink_dev *cb = params->cb;
1716 REG_WR(cb, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1718 REG_WR(cb, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1720 REG_WR(cb, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1728 struct elink_dev *cb = params->cb;
1729 if (!(REG_RD(cb, MISC_REG_RESET_REG_2) &
1732 val = REG_RD(cb, umac_base + UMAC_REG_COMMAND_CONFIG);
1740 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1748 struct elink_dev *cb = params->cb;
1750 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1752 MSLEEP(cb, 1);
1754 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1757 ELINK_DEBUG_P0(cb, "enabling UMAC\n");
1760 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1780 ELINK_DEBUG_P1(cb, "Invalid speed for UMAC %d\n",
1793 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1794 USLEEP(cb, 50);
1798 ELINK_DEBUG_P0(cb, "configured UMAC for EEE\n");
1799 REG_WR(cb, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1801 REG_WR(cb, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1803 REG_WR(cb, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1807 REG_WR(cb, umac_base + UMAC_REG_MAC_ADDR0,
1812 REG_WR(cb, umac_base + UMAC_REG_MAC_ADDR1,
1820 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1821 USLEEP(cb, 50);
1829 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1834 REG_WR(cb, umac_base + UMAC_REG_MAXFR, 0x2710);
1844 struct elink_dev *cb = params->cb;
1845 u32 is_port4mode = elink_is_4_port_mode(cb);
1857 (REG_RD(cb, MISC_REG_RESET_REG_2) &
1859 ELINK_DEBUG_P0(cb,
1865 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1867 MSLEEP(cb, 1);
1869 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1872 ELINK_DEBUG_P0(cb, "Init XMAC to 2 ports x 10G per path\n");
1875 REG_WR(cb, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1878 REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1881 REG_WR(cb, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1883 ELINK_DEBUG_P0(cb,
1886 REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1888 ELINK_DEBUG_P0(cb,
1891 REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1895 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1897 MSLEEP(cb, 1);
1899 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1907 struct elink_dev *cb = params->cb;
1911 if (REG_RD(cb, MISC_REG_RESET_REG_2) &
1917 pfc_ctrl = REG_RD(cb, xmac_base + XMAC_REG_PFC_CTRL_HI);
1918 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI,
1920 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI,
1922 ELINK_DEBUG_P1(cb, "Disable XMAC on port %x\n", port);
1923 val = REG_RD(cb, xmac_base + XMAC_REG_CTRL);
1928 REG_WR(cb, xmac_base + XMAC_REG_CTRL, val);
1936 struct elink_dev *cb = params->cb;
1937 ELINK_DEBUG_P0(cb, "enabling XMAC\n");
1950 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1956 REG_WR(cb, xmac_base + XMAC_REG_RX_LSS_CTRL,
1959 REG_WR(cb, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1960 REG_WR(cb, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1965 REG_WR(cb, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1968 REG_WR(cb, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1974 ELINK_DEBUG_P0(cb, "Setting XMAC for EEE\n");
1975 REG_WR(cb, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1976 REG_WR(cb, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1978 REG_WR(cb, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1993 REG_WR(cb, xmac_base + XMAC_REG_CTRL, val);
2007 struct elink_dev *cb = params->cb;
2012 ELINK_DEBUG_P0(cb, "enabling EMAC\n");
2015 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2019 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
2025 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2026 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2034 ELINK_DEBUG_P0(cb, "elink_emac_enable: Setting FPGA\n");
2036 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2037 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2046 ELINK_DEBUG_P0(cb, "XGXS\n");
2048 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
2050 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2053 ELINK_DEBUG_P0(cb, "SerDes\n");
2055 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2058 elink_bits_en(cb, emac_base + EMAC_REG_EMAC_RX_MODE,
2060 elink_bits_en(cb, emac_base + EMAC_REG_EMAC_TX_MODE,
2066 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE);
2067 EMAC_WR(cb, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
2071 elink_bits_dis(cb, emac_base + EMAC_REG_EMAC_RX_MODE,
2074 elink_bits_dis(cb, emac_base + EMAC_REG_EMAC_TX_MODE,
2080 elink_bits_en(cb, emac_base +
2085 elink_bits_en(cb, emac_base +
2090 elink_bits_en(cb, emac_base + EMAC_REG_EMAC_TX_MODE,
2097 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_RX_MODE);
2107 EMAC_WR(cb, EMAC_REG_RX_PFC_MODE, 0);
2109 ELINK_DEBUG_P0(cb, "PFC is enabled\n");
2111 EMAC_WR(cb, EMAC_REG_RX_PFC_MODE,
2116 EMAC_WR(cb, EMAC_REG_RX_PFC_PARAM,
2123 EMAC_WR(cb, EMAC_REG_EMAC_RX_MODE, val);
2126 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE);
2131 EMAC_WR(cb, EMAC_REG_EMAC_MODE, val);
2134 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 1);
2138 EMAC_WR(cb, EMAC_REG_EMAC_RX_MTU_SIZE,
2144 REG_WR(cb, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2147 REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2148 REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2149 REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2152 REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2159 REG_WR(cb, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2160 REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2165 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2169 REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2172 REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
2184 struct elink_dev *cb = params->cb;
2196 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
2206 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2219 struct elink_dev *cb = params->cb;
2231 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2232 USLEEP(cb, 30);
2242 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2245 ELINK_DEBUG_P0(cb, "PFC is enabled\n");
2254 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2259 ELINK_DEBUG_P0(cb, "PFC is disabled\n");
2265 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2278 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2285 ELINK_DEBUG_P0(cb, "enable bmac loopback\n");
2293 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2304 static elink_status_t elink_pfc_nig_rx_priority_mask(struct elink_dev *cb,
2343 REG_WR(cb, nig_reg_rx_priority_mask_add, priority_mask);
2351 struct elink_dev *cb = params->cb;
2353 REG_WR(cb, params->shmem_base +
2366 struct elink_dev *cb = params->cb;
2371 ELINK_DEBUG_P0(cb, "updating pfc nig parameters\n");
2377 xcm_mask = REG_RD(cb, port ? NIG_REG_LLH1_XCM_MASK :
2408 REG_WR(cb, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2410 REG_WR(cb, port ? NIG_REG_LLFC_OUT_EN_1 :
2412 REG_WR(cb, port ? NIG_REG_LLFC_ENABLE_1 :
2414 REG_WR(cb, port ? NIG_REG_PAUSE_ENABLE_1 :
2417 REG_WR(cb, port ? NIG_REG_PPP_ENABLE_1 :
2420 REG_WR(cb, port ? NIG_REG_LLH1_XCM_MASK :
2423 REG_WR(cb, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2427 REG_WR(cb, port ? NIG_REG_XCM1_OUT_EN :
2431 REG_WR(cb, port ? NIG_REG_P1_HWPFC_ENABLE :
2439 elink_pfc_nig_rx_priority_mask(cb, i,
2442 REG_WR(cb, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2446 REG_WR(cb, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2450 REG_WR(cb, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2464 struct elink_dev *cb = params->cb;
2480 ELINK_DEBUG_P0(cb, "About to update PFC in BMAC\n");
2486 val = REG_RD(cb, MISC_REG_RESET_REG_2);
2490 ELINK_DEBUG_P0(cb, "About to update PFC in EMAC\n");
2504 REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2515 struct elink_dev *cb = params->cb;
2522 ELINK_DEBUG_P0(cb, "Enabling BigMAC1\n");
2527 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2537 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2543 ELINK_DEBUG_P0(cb, "enable bmac loopback\n");
2547 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2552 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2559 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2564 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2569 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2576 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
2590 struct elink_dev *cb = params->cb;
2596 ELINK_DEBUG_P0(cb, "Enabling BigMAC2\n");
2600 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2601 USLEEP(cb, 30);
2606 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2609 USLEEP(cb, 30);
2618 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2621 USLEEP(cb, 30);
2626 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2628 USLEEP(cb, 30);
2633 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2634 USLEEP(cb, 30);
2639 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2640 USLEEP(cb, 30);
2644 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2645 USLEEP(cb, 30);
2659 struct elink_dev *cb = params->cb;
2663 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2665 MSLEEP(cb, 1);
2668 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2672 REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2687 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2688 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2689 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2695 REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2696 REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2697 REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2698 REG_WR(cb, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2699 REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2700 REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2708 static void elink_set_bmac_rx(struct elink_dev *cb, u32 chip_id, u8 port, u8 en)
2713 u32 nig_bmac_enable = REG_RD(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2720 if (REG_RD(cb, MISC_REG_RESET_REG_2) &
2724 REG_RD_DMAE(cb, bmac_addr, wb_data, 2);
2729 REG_WR_DMAE(cb, bmac_addr, wb_data, 2);
2730 MSLEEP(cb, 1);
2740 struct elink_dev *cb = params->cb;
2746 REG_WR(cb, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2749 init_crd = REG_RD(cb, PBF_REG_P0_INIT_CRD + port*4);
2750 crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8);
2751 ELINK_DEBUG_P2(cb, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2754 MSLEEP(cb, 5);
2755 crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8);
2758 crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8);
2760 ELINK_DEBUG_P2(cb, "BUG! init_crd 0x%x != crd 0x%x\n",
2770 REG_WR(cb, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2772 REG_WR(cb, PBF_REG_P0_ARB_THRSH + port*4, 0);
2779 REG_WR(cb, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2781 REG_WR(cb, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2788 ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n",
2793 REG_WR(cb, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2794 ELINK_DEBUG_P2(cb, "PBF updated to speed %d credit %d\n",
2798 REG_WR(cb, PBF_REG_INIT_P0 + port*4, 0x1);
2799 MSLEEP(cb, 5);
2800 REG_WR(cb, PBF_REG_INIT_P0 + port*4, 0x0);
2803 REG_WR(cb, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2824 static u32 elink_get_emac_base(struct elink_dev *cb,
2832 if (REG_RD(cb, NIG_REG_PORT_SWAP))
2838 if (REG_RD(cb, NIG_REG_PORT_SWAP))
2862 static elink_status_t elink_cl22_write(struct elink_dev *cb,
2870 mode = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2871 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2878 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2881 USLEEP(cb, 10);
2883 tmp = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2885 USLEEP(cb, 5);
2890 ELINK_DEBUG_P0(cb, "write phy register failed\n");
2893 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2897 static elink_status_t elink_cl22_read(struct elink_dev *cb,
2906 mode = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2907 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2914 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2917 USLEEP(cb, 10);
2919 val = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2922 USLEEP(cb, 5);
2927 ELINK_DEBUG_P0(cb, "read phy register failed\n");
2932 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2941 static elink_status_t elink_cl45_read(struct elink_dev *cb, struct elink_phy *phy,
2950 chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) |
2951 ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12);
2952 elink_set_mdio_clk(cb, chip_id, phy->mdio_ctrl);
2957 elink_bits_en(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2963 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2966 USLEEP(cb, 10);
2968 val = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2970 USLEEP(cb, 5);
2975 ELINK_DEBUG_P0(cb, "read phy register failed\n");
2976 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
2985 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2988 USLEEP(cb, 10);
2990 val = REG_RD(cb, phy->mdio_ctrl +
2998 ELINK_DEBUG_P0(cb, "read phy register failed\n");
2999 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3010 elink_cl45_read(cb, phy, devad, 0xf, &temp_val);
3015 elink_bits_dis(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3020 static elink_status_t elink_cl45_write(struct elink_dev *cb, struct elink_phy *phy,
3029 chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) |
3030 ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12);
3031 elink_set_mdio_clk(cb, chip_id, phy->mdio_ctrl);
3036 elink_bits_en(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3043 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3046 USLEEP(cb, 10);
3048 tmp = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3050 USLEEP(cb, 5);
3055 ELINK_DEBUG_P0(cb, "write phy register failed\n");
3056 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3064 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3067 USLEEP(cb, 10);
3069 tmp = REG_RD(cb, phy->mdio_ctrl +
3072 USLEEP(cb, 5);
3077 ELINK_DEBUG_P0(cb, "write phy register failed\n");
3078 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3088 elink_cl45_read(cb, phy, devad, 0xf, &temp_val);
3092 elink_bits_dis(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3104 struct elink_dev *cb = params->cb;
3106 if (REG_RD(cb, params->shmem2_base) <=
3156 struct elink_dev *cb = params->cb;
3171 eee_mode = ((REG_RD(cb, params->shmem_base +
3189 struct elink_dev *cb = params->cb;
3194 REG_WR(cb, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
3199 ELINK_DEBUG_P0(cb, "Error: Tx LPI is enabled with timer 0\n");
3241 struct elink_dev *cb = params->cb;
3244 REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3246 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3257 struct elink_dev *cb = params->cb;
3261 REG_WR(cb, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3264 ELINK_DEBUG_P0(cb, "Advertise 10GBase-T EEE\n");
3268 ELINK_DEBUG_P0(cb, "Advertise 1GBase-T EEE\n");
3272 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3282 struct elink_dev *cb = params->cb;
3285 REG_WR(cb, params->shmem2_base +
3294 struct elink_dev *cb = params->cb;
3299 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3300 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3307 ELINK_DEBUG_P0(cb, "EEE negotiated - 100M\n");
3315 ELINK_DEBUG_P0(cb, "EEE negotiated - 1G\n");
3323 ELINK_DEBUG_P0(cb, "EEE negotiated - 10G\n");
3331 ELINK_DEBUG_P0(cb, "EEE is active\n");
3344 struct elink_dev *cb = params->cb;
3347 board_cfg = REG_RD(cb, params->shmem_base +
3355 sfp_ctrl = REG_RD(cb, params->shmem_base +
3360 ELINK_DEBUG_P0(cb, "Setting BSC switch\n");
3362 elink_set_cfg_pin(cb, i2c_pins[idx], i2c_val[idx]);
3366 struct elink_dev *cb,
3377 ELINK_DEBUG_P1(cb, "invalid xfer_cnt %d. Max is 16 bytes\n",
3387 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND);
3389 REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val);
3393 REG_WR(cb, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3400 REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val);
3404 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND);
3406 USLEEP(cb, 10);
3407 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND);
3409 ELINK_DEBUG_P1(cb, "wr 0 byte timed out after %d try\n",
3424 REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val);
3428 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND);
3430 USLEEP(cb, 10);
3431 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND);
3433 ELINK_DEBUG_P1(cb, "rd op timed out after %d try\n", i);
3442 data_array[i] = REG_RD(cb, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3456 static void elink_cl45_read_or_write(struct elink_dev *cb, struct elink_phy *phy,
3460 elink_cl45_read(cb, phy, devad, reg, &val);
3461 elink_cl45_write(cb, phy, devad, reg, val | or_val);
3464 static void elink_cl45_read_and_write(struct elink_dev *cb,
3469 elink_cl45_read(cb, phy, devad, reg, &val);
3470 elink_cl45_write(cb, phy, devad, reg, val & and_val);
3484 return elink_cl45_read(params->cb,
3501 return elink_cl45_write(params->cb,
3516 struct elink_dev *cb = params->cb;
3520 path = PATH_ID(cb);
3523 if (elink_is_4_port_mode(cb)) {
3527 path_swap_ovr = REG_RD(cb, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3531 path_swap = REG_RD(cb, MISC_REG_FOUR_PORT_PATH_SWAP);
3537 port_swap_ovr = REG_RD(cb, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3541 port_swap = REG_RD(cb, MISC_REG_FOUR_PORT_PORT_SWAP);
3551 REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3556 REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP);
3573 struct elink_dev *cb = params->cb;
3596 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
3607 static void elink_set_serdes_access(struct elink_dev *cb, u8 port)
3612 REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3613 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3614 USLEEP(cb, 500);
3615 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3616 USLEEP(cb, 500);
3618 REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3621 static void elink_serdes_deassert(struct elink_dev *cb, u8 port)
3625 ELINK_DEBUG_P0(cb, "elink_serdes_deassert\n");
3630 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3631 USLEEP(cb, 500);
3632 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3634 elink_set_serdes_access(cb, port);
3636 REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3647 struct elink_dev *cb = params->cb;
3651 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3652 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3660 struct elink_dev *cb = params->cb;
3663 ELINK_DEBUG_P0(cb, "elink_xgxs_deassert\n");
3669 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3670 USLEEP(cb, 500);
3671 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3681 struct elink_dev *cb = params->cb;
3717 ELINK_DEBUG_P1(cb, "ieee_fc = 0x%x\n", *ieee_fc);
3725 struct elink_dev *cb = params->cb;
3756 ELINK_DEBUG_P3(cb, "req_flow_ctrl %x, req_line_speed %x,"
3770 struct elink_dev *cb = params->cb;
3772 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3788 ELINK_DEBUG_P1(cb, "Ext phy AN advertize 0x%x\n", val);
3789 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3827 struct elink_dev *cb = params->cb;
3830 elink_cl22_read(cb, phy, 0x4, &ld_pause);
3831 elink_cl22_read(cb, phy, 0x5, &lp_pause);
3837 elink_cl45_read(cb, phy,
3844 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
3846 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
3849 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
3851 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
3861 elink_cl45_read(cb, phy,
3864 elink_cl45_read(cb, phy,
3872 ELINK_DEBUG_P1(cb, "Ext PHY pause result 0x%x\n", pause_result);
3920 struct elink_dev *cb = params->cb;
3922 if (SHMEM2_HAS(cb, params->shmem2_base, link_attr_sync))
3923 REG_WR(cb, params->shmem2_base +
3932 struct elink_dev *cb = params->cb;
3953 ELINK_DEBUG_P0(cb, "Enabling 20G-KR2\n");
3955 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
3959 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
3971 struct elink_dev *cb = params->cb;
3991 ELINK_DEBUG_P0(cb, "Disabling 20G-KR2\n");
3994 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
4005 struct elink_dev *cb = params->cb;
4007 ELINK_DEBUG_P0(cb, "Configure WC for LPI pass through\n");
4008 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4010 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4018 struct elink_dev *cb = params->cb;
4020 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
4022 elink_cl45_write(cb, phy, MDIO_AN_DEVAD,
4034 struct elink_dev *cb = params->cb;
4045 ELINK_DEBUG_P0(cb, "Enable Auto Negotiation for KR\n");
4048 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
4051 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4055 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4066 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, addr, 0x1);
4067 ELINK_DEBUG_P0(cb, "Advertize 1G\n");
4075 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
4078 elink_cl45_write(cb, phy, MDIO_AN_DEVAD,
4081 ELINK_DEBUG_P0(cb, "Advertize 10G\n");
4086 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4091 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4094 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4097 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4102 elink_cl45_write(cb, phy, MDIO_AN_DEVAD,
4106 elink_cl45_write(cb, phy, MDIO_AN_DEVAD,
4112 if (REG_RD(cb, params->shmem_base +
4116 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4119 ELINK_DEBUG_P0(cb, "Enable CL37 BAM on KR\n");
4125 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4129 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4136 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
4139 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4143 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4150 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4152 wc_lane_config = REG_RD(cb, params->shmem_base +
4155 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4170 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4185 struct elink_dev *cb = params->cb;
4201 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
4206 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
4209 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4212 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4215 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4218 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4223 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD,
4226 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD,
4230 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4234 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4238 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4242 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4244 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4253 struct elink_dev *cb = params->cb;
4258 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4262 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4266 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4269 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
4273 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4277 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
4281 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
4286 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4288 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4293 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4303 cfg_tap_val = REG_RD(cb, params->shmem_base +
4328 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4333 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4336 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4341 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4345 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4351 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4355 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
4359 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
4369 struct elink_dev *cb = params->cb;
4371 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
4375 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
4380 elink_cl45_read_and_write(cb, phy, MDIO_PMA_DEVAD,
4382 elink_cl45_write(cb, phy, MDIO_AN_DEVAD,
4385 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4389 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4393 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4396 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4399 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4403 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4405 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4409 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
4412 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4420 static void elink_warpcore_set_20G_DXGXS(struct elink_dev *cb,
4425 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4429 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4432 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4435 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4438 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4441 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4444 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4447 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4450 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4453 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4457 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4461 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4465 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4469 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4481 struct elink_dev *cb = params->cb;
4485 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
4492 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4495 ELINK_DEBUG_P0(cb, "set SGMII AUTONEG\n");
4497 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4510 ELINK_DEBUG_P1(cb,
4518 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4521 ELINK_DEBUG_P1(cb, "set SGMII force speed %d\n",
4523 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4525 ELINK_DEBUG_P1(cb, " (readback) %x\n", val16);
4529 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4536 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4541 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4543 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4548 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4553 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4560 static void elink_warpcore_reset_lane(struct elink_dev *cb,
4566 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4572 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4574 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4584 struct elink_dev *cb = params->cb;
4603 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4607 elink_cl45_write(cb, phy, wc_regs[i].devad, wc_regs[i].reg,
4611 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4616 static elink_status_t elink_get_mod_abs_int_cfg(struct elink_dev *cb,
4625 cfg_pin = (REG_RD(cb, shmem_base +
4639 ELINK_DEBUG_P1(cb,
4658 struct elink_dev *cb = params->cb;
4661 if (elink_get_mod_abs_int_cfg(cb, params->chip_id,
4665 gpio_val = ELINK_GET_GPIO(cb, gpio_num, gpio_port);
4677 struct elink_dev *cb = params->cb;
4681 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4692 struct elink_dev *cb = params->cb;
4703 serdes_net_if = (REG_RD(cb, params->shmem_base +
4711 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 0x81d1,
4721 elink_warpcore_reset_lane(cb, phy, 1);
4722 elink_warpcore_reset_lane(cb, phy, 0);
4725 elink_cl45_write(cb, phy, MDIO_AN_DEVAD,
4729 ELINK_DEBUG_P1(cb, "0x%x retry left\n",
4747 struct elink_dev *cb = params->cb;
4753 ELINK_DEBUG_P0(cb, "Setting 10G SFI\n");
4756 ELINK_DEBUG_P0(cb, "Setting 1G Fiber\n");
4765 struct elink_dev *cb = params->cb;
4769 cfg_pin = REG_RD(cb, params->shmem_base +
4774 ELINK_DEBUG_P1(cb, "Setting WC TX to %d\n", tx_en);
4777 elink_set_cfg_pin(cb, cfg_pin, tx_en ^ 1);
4779 elink_set_cfg_pin(cb, cfg_pin + 3, tx_en ^ 1);
4786 struct elink_dev *cb = params->cb;
4790 serdes_net_if = (REG_RD(cb, params->shmem_base +
4794 ELINK_DEBUG_P2(cb, "Begin Warpcore init, link_speed %d, "
4798 elink_warpcore_reset_lane(cb, phy, 1);
4805 ELINK_DEBUG_P0(cb, "Setting SGMII mode\n");
4815 ELINK_DEBUG_P0(cb, "Setting KR 10G-Force\n");
4823 ELINK_DEBUG_P0(cb, "Setting 10G XFI\n");
4827 ELINK_DEBUG_P0(cb, "1G Fiber\n");
4830 ELINK_DEBUG_P0(cb, "10/100/1G SGMII\n");
4861 ELINK_DEBUG_P0(cb, "Speed not supported yet\n");
4864 ELINK_DEBUG_P0(cb, "Setting 20G DXGXS\n");
4865 elink_warpcore_set_20G_DXGXS(cb, phy, lane);
4876 ELINK_DEBUG_P0(cb, "Setting KR 20G-Force\n");
4882 ELINK_DEBUG_P1(cb,
4890 elink_warpcore_reset_lane(cb, phy, 0);
4891 ELINK_DEBUG_P0(cb, "Exit config init\n");
4898 struct elink_dev *cb = params->cb;
4901 elink_set_mdio_emac_per_phy(cb, params);
4904 elink_warpcore_reset_lane(cb, phy, 1);
4908 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
4911 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
4915 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
4918 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
4922 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
4926 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4931 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4934 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4943 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4955 struct elink_dev *cb = params->cb;
4958 ELINK_DEBUG_P2(cb, "Setting Warpcore loopback type %x, speed %d\n",
4966 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
4969 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4974 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
4979 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
4987 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4990 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
4999 static void elink_warpcore_powerdown_secondport_lanes(struct elink_dev *cb,
5005 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5007 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5011 path_swap_ovr = REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
5015 path_swap = REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP);
5033 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5039 cb, phy, MDIO_WC_DEVAD,
5051 * @param cb
5063 static void elink_warpcore_sequencer(struct elink_dev *cb,
5068 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
5074 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5078 static void elink_warpcore_set_lane_swap(struct elink_dev *cb,
5092 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
5096 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5100 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
5104 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5108 static void elink_warpcore_set_lane_polarity(struct elink_dev *cb,
5114 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5117 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5120 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5123 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5127 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5130 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5133 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5136 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5140 static elink_status_t elink_reset_warpcore(struct elink_dev *cb)
5144 ELINK_DEBUG_P0(cb, "Resetting Warpcore\n");
5146 REG_WR(cb, MISC_REG_WC0_RESET, 0xE);
5147 MSLEEP(cb, 1);
5148 REG_WR(cb, MISC_REG_WC0_RESET, 0xF);
5151 MSLEEP(cb, 1);
5152 pll_lock = REG_RD(cb, MISC_REG_WC0_PLL_LOCK);
5155 REG_WR(cb, MISC_REG_WC0_RESET, 0x3FF);
5160 ELINK_DEBUG_P0(cb, "BUG! WARPCORE is still in reset!\n");
5168 static void elink_warpcore_set_quad_mode(struct elink_dev *cb,
5174 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
5177 elink_warpcore_reset_lane(cb, phy, 1);
5179 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
5182 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5186 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5190 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5198 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5204 static void elink_warpcore_set_dual_mode(struct elink_dev *cb,
5211 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
5214 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
5217 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5220 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5229 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5235 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
5241 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5245 serdes_net_if = (REG_RD(cb, shmem_base +
5252 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
5254 elink_warpcore_reset_lane(cb, phy, 1);
5256 elink_warpcore_set_20G_DXGXS(cb, phy, lane);
5258 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5260 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD,
5264 static elink_status_t elink_warpcore_load_uc(struct elink_dev *cb,
5268 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
5272 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5275 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5279 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5284 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
5288 USLEEP(cb, 1);
5293 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, MDIO_WC_REG_UC_INFO_B1_CRC, 0);
5298 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5302 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD,
5306 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
5309 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
5313 MSLEEP(cb, 1);
5326 struct elink_dev *cb = params->cb;
5333 ELINK_DEBUG_P0(cb, "phy link up\n");
5415 ELINK_DEBUG_P0(cb, "phy link down\n");
5435 struct elink_dev *cb = params->cb;
5441 vars->link_status = REG_RD(cb, params->shmem_base +
5453 vars->eee_status = REG_RD(cb, params->shmem2_base +
5465 media_types = REG_RD(cb, sync_offset);
5476 ELINK_DEBUG_P1(cb, "media_types = 0x%x\n", media_types);
5483 vars->aeu_int_mask = REG_RD(cb, sync_offset);
5493 if (SHMEM2_HAS(cb, params->shmem2_base, link_attr_sync))
5494 params->link_attr_sync = SHMEM2_RD(cb, params->shmem2_base,
5497 ELINK_DEBUG_P3(cb, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
5499 ELINK_DEBUG_P3(cb, "line_speed %x duplex %x flow_ctrl 0x%x\n",
5508 struct elink_dev *cb = params->cb;
5515 CL22_RD_OVER_CL45(cb, phy,
5520 CL22_WR_OVER_CL45(cb, phy,
5530 struct elink_dev *cb = params->cb;
5533 CL22_RD_OVER_CL45(cb, phy,
5538 CL22_WR_OVER_CL45(cb, phy,
5545 elink_set_serdes_access(cb, params->port);
5550 USLEEP(cb, 5);
5553 CL22_RD_OVER_CL45(cb, phy,
5559 USLEEP(cb, 5);
5564 elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
5567 ELINK_DEBUG_P0(cb, "BUG! XGXS is still in reset!\n");
5575 struct elink_dev *cb = params->cb;
5589 CL22_WR_OVER_CL45(cb, phy,
5596 CL22_WR_OVER_CL45(cb, phy,
5602 CL22_WR_OVER_CL45(cb, phy,
5608 CL22_WR_OVER_CL45(cb, phy,
5617 struct elink_dev *cb = params->cb;
5619 CL22_RD_OVER_CL45(cb, phy,
5627 ELINK_DEBUG_P2(cb, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
5629 CL22_WR_OVER_CL45(cb, phy,
5637 ELINK_DEBUG_P0(cb, "XGXS\n");
5639 CL22_WR_OVER_CL45(cb, phy,
5644 CL22_RD_OVER_CL45(cb, phy,
5653 CL22_WR_OVER_CL45(cb, phy,
5659 CL22_WR_OVER_CL45(cb, phy,
5672 struct elink_dev *cb = params->cb;
5676 CL22_RD_OVER_CL45(cb, phy,
5687 CL22_WR_OVER_CL45(cb, phy,
5693 CL22_RD_OVER_CL45(cb, phy,
5704 CL22_WR_OVER_CL45(cb, phy,
5709 CL22_RD_OVER_CL45(cb, phy,
5722 CL22_WR_OVER_CL45(cb, phy,
5729 CL22_WR_OVER_CL45(cb, phy,
5735 CL22_WR_OVER_CL45(cb, phy,
5743 CL22_RD_OVER_CL45(cb, phy,
5754 CL22_WR_OVER_CL45(cb, phy,
5765 CL22_WR_OVER_CL45(cb, phy,
5775 struct elink_dev *cb = params->cb;
5779 CL22_RD_OVER_CL45(cb, phy,
5787 CL22_WR_OVER_CL45(cb, phy,
5794 CL22_RD_OVER_CL45(cb, phy,
5798 ELINK_DEBUG_P1(cb, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5814 CL22_WR_OVER_CL45(cb, phy,
5823 struct elink_dev *cb = params->cb;
5831 CL22_WR_OVER_CL45(cb, phy,
5835 CL22_WR_OVER_CL45(cb, phy,
5844 struct elink_dev *cb = params->cb;
5848 CL22_WR_OVER_CL45(cb, phy,
5851 CL22_RD_OVER_CL45(cb, phy,
5856 CL22_WR_OVER_CL45(cb, phy,
5865 struct elink_dev *cb = params->cb;
5868 ELINK_DEBUG_P0(cb, "elink_restart_autoneg\n");
5872 CL22_RD_OVER_CL45(cb, phy,
5877 CL22_WR_OVER_CL45(cb, phy,
5885 CL22_RD_OVER_CL45(cb, phy,
5889 ELINK_DEBUG_P1(cb,
5892 CL22_WR_OVER_CL45(cb, phy,
5905 struct elink_dev *cb = params->cb;
5910 CL22_RD_OVER_CL45(cb, phy,
5919 CL22_WR_OVER_CL45(cb, phy,
5929 CL22_RD_OVER_CL45(cb, phy,
5951 ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n",
5960 CL22_WR_OVER_CL45(cb, phy,
5976 struct elink_dev *cb = params->cb;
5980 CL22_RD_OVER_CL45(cb, phy,
5984 CL22_RD_OVER_CL45(cb, phy,
5989 ELINK_DEBUG_P1(cb, "1G parallel detect link on port %d\n",
5994 CL22_RD_OVER_CL45(cb, phy,
6000 ELINK_DEBUG_P1(cb, "10G parallel detect link on port %d\n",
6015 struct elink_dev *cb = params->cb;
6022 CL22_RD_OVER_CL45(cb, phy,
6026 CL22_RD_OVER_CL45(cb, phy,
6034 ELINK_DEBUG_P1(cb, "pause_result CL73 0x%x\n", pause_result);
6036 CL22_RD_OVER_CL45(cb, phy,
6040 CL22_RD_OVER_CL45(cb, phy,
6048 ELINK_DEBUG_P1(cb, "pause_result CL37 0x%x\n", pause_result);
6060 struct elink_dev *cb = params->cb;
6081 ELINK_DEBUG_P1(cb, "flow_ctrl 0x%x\n", vars->flow_ctrl);
6087 struct elink_dev *cb = params->cb;
6089 ELINK_DEBUG_P0(cb, "elink_check_fallback_to_cl37\n");
6091 CL22_RD_OVER_CL45(cb, phy,
6097 ELINK_DEBUG_P1(cb, "Signal is not detected. Restoring CL73."
6099 CL22_WR_OVER_CL45(cb, phy,
6106 CL22_RD_OVER_CL45(cb, phy,
6115 ELINK_DEBUG_P1(cb, "CL73 state-machine is not stable. "
6122 CL22_RD_OVER_CL45(cb, phy,
6131 ELINK_DEBUG_P1(cb, "No CL37 FSM were received. "
6143 CL22_WR_OVER_CL45(cb, phy,
6149 ELINK_DEBUG_P0(cb, "Disabling CL73, and restarting CL37 autoneg\n");
6174 struct elink_dev *cb = params->cb;
6179 ELINK_DEBUG_P0(cb, "phy link up\n");
6220 ELINK_DEBUG_P1(cb,
6240 ELINK_DEBUG_P1(cb,
6246 ELINK_DEBUG_P0(cb, "phy link down\n");
6254 ELINK_DEBUG_P2(cb, " phy_link_up %x line_speed %d\n",
6264 struct elink_dev *cb = params->cb;
6270 CL22_RD_OVER_CL45(cb, phy,
6279 ELINK_DEBUG_P3(cb, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
6307 CL22_RD_OVER_CL45(cb, phy, MDIO_REG_BANK_CL73_IEEEB1,
6318 CL22_RD_OVER_CL45(cb, phy, MDIO_REG_BANK_OVER_1G,
6329 ELINK_DEBUG_P3(cb, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6340 struct elink_dev *cb = params->cb;
6348 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
6350 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
6356 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
6358 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
6360 ELINK_DEBUG_P2(cb, "PCS RX link status = 0x%x-->0x%x\n",
6366 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
6369 ELINK_DEBUG_P1(cb, "0x81d1 = 0x%x\n", gp_status1);
6377 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
6379 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
6387 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
6395 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
6411 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
6422 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
6436 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
6439 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
6442 ELINK_DEBUG_P2(cb, "lane %d gp_speed 0x%x\n", lane, gp_speed);
6458 ELINK_DEBUG_P3(cb, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6466 struct elink_dev *cb = params->cb;
6473 CL22_RD_OVER_CL45(cb, phy,
6487 CL22_RD_OVER_CL45(cb, phy,
6496 CL22_WR_OVER_CL45(cb, phy,
6506 struct elink_dev *cb = params->cb;
6510 ELINK_DEBUG_P0(cb, "setting link speed & duplex\n");
6511 elink_bits_dis(cb, GRCBASE_EMAC0 + port*0x400 +
6535 ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n",
6542 elink_bits_en(cb,
6555 struct elink_dev *cb = params->cb;
6559 CL22_WR_OVER_CL45(cb, phy,
6567 CL22_WR_OVER_CL45(cb, phy,
6579 struct elink_dev *cb = params->cb;
6593 ELINK_DEBUG_P0(cb, "not SGMII, no AN\n");
6602 ELINK_DEBUG_P0(cb, "not SGMII, AN\n");
6619 ELINK_DEBUG_P0(cb, "SGMII\n");
6668 static u16 elink_wait_reset_complete(struct elink_dev *cb,
6677 elink_cl22_read(cb, phy,
6681 elink_cl45_read(cb, phy,
6686 MSLEEP(cb, 1);
6690 elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
6693 ELINK_DEBUG_P2(cb, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6702 struct elink_dev *cb = params->cb;
6712 ELINK_DEBUG_P0(cb, "enabled XGXS interrupt\n");
6717 ELINK_DEBUG_P0(cb, "enabled external phy int\n");
6722 ELINK_DEBUG_P0(cb, "enabled SerDes interrupt\n");
6727 ELINK_DEBUG_P0(cb, "enabled external phy int\n");
6730 elink_bits_en(cb,
6734 ELINK_DEBUG_P3(cb, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6736 REG_RD(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6737 ELINK_DEBUG_P3(cb, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6738 REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6739 REG_RD(cb, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6740 REG_RD(cb, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6741 ELINK_DEBUG_P2(cb, " 10G %x, XGXS_LINK %x\n",
6742 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6743 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6746 static void elink_rearm_latch_signal(struct elink_dev *cb, u8 port,
6756 latch_status = REG_RD(cb,
6758 ELINK_DEBUG_P1(cb, "latch_status = 0x%x\n", latch_status);
6761 elink_bits_en(cb,
6766 elink_bits_dis(cb,
6774 REG_WR(cb, NIG_REG_LATCH_STATUS_0 + port*8,
6783 struct elink_dev *cb = params->cb;
6789 elink_bits_dis(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6812 ELINK_DEBUG_P1(cb, "Ack link up interrupt with mask 0x%x\n",
6814 elink_bits_en(cb,
6878 struct elink_dev *cb;
6885 cb = params->cb;
6889 spirom_ver = REG_RD(cb, params->phy[ELINK_EXT_PHY1].ver_addr);
6899 spirom_ver = REG_RD(cb, params->phy[ELINK_EXT_PHY2].ver_addr);
6922 struct elink_dev *cb = params->cb;
6927 ELINK_DEBUG_P0(cb, "XGXS 10G loopback enable\n");
6931 md_devad = REG_RD(cb, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6934 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6938 elink_cl45_write(cb, phy,
6944 elink_cl45_write(cb, phy,
6949 MSLEEP(cb, 200);
6955 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6960 ELINK_DEBUG_P0(cb, "XGXS 1G loopback enable\n");
6961 elink_cl45_read(cb, phy, 5,
6965 elink_cl45_write(cb, phy, 5,
6984 struct elink_dev *cb = params->cb;
6985 ELINK_DEBUG_P2(cb, "elink_set_led: port %x, mode %d\n", port, mode);
6986 ELINK_DEBUG_P2(cb, "speed 0x%x, hw_led_mode 0x%x\n",
7004 REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 0);
7005 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4,
7008 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED);
7017 EMAC_WR(cb, EMAC_REG_EMAC_LED, tmp);
7035 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0);
7036 REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 1);
7038 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED);
7039 EMAC_WR(cb, EMAC_REG_EMAC_LED,
7056 REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 1);
7061 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0);
7063 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4,
7068 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0);
7069 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED);
7070 EMAC_WR(cb, EMAC_REG_EMAC_LED, tmp |
7082 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4,
7086 REG_WR(cb, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
7089 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7092 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7094 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
7096 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED);
7097 EMAC_WR(cb, EMAC_REG_EMAC_LED,
7107 REG_WR(cb, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
7109 REG_WR(cb, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
7111 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
7119 ELINK_DEBUG_P1(cb, "elink_set_led: Invalid led mode %d\n",
7135 struct elink_dev *cb = params->cb;
7154 elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD,
7156 elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD,
7162 elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD,
7172 CL22_RD_OVER_CL45(cb, int_phy,
7227 struct elink_dev *cb = params->cb;
7286 ELINK_DEBUG_P0(cb,
7296 elink_bits_dis(cb, NIG_REG_STATUS_INTERRUPT_PORT0 +
7311 REG_WR(params->cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
7322 struct elink_dev *cb = params->cb;
7326 gpio_port = PATH_ID(cb);
7329 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1,
7332 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2,
7335 ELINK_DEBUG_P0(cb, "reset external PHY\n");
7343 struct elink_dev *cb = params->cb;
7346 ELINK_DEBUG_P1(cb, "Port %x: Link is down\n", port);
7358 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7362 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7364 MSLEEP(cb, 10);
7369 elink_set_bmac_rx(cb, params->chip_id, params->port, 0);
7375 REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
7377 REG_WR(cb, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
7395 struct elink_dev *cb = params->cb;
7415 ELINK_DEBUG_P0(cb, "Found errors on XMAC\n");
7427 ELINK_DEBUG_P0(cb, "Enabling LPI assertion\n");
7428 REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
7430 REG_WR(cb, MISC_REG_CPMU_LP_DR_ENABLE, 1);
7431 REG_WR(cb, MISC_REG_CPMU_LP_MASK_ENT_P0 +
7442 ELINK_DEBUG_P0(cb, "Found errors on BMAC\n");
7472 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
7486 MSLEEP(cb, 20);
7492 struct elink_dev *cb = params->cb;
7496 if (!(SHMEM2_HAS(cb, params->shmem2_base, link_change_count)))
7504 val = REG_RD(cb, addr) + 1;
7505 REG_WR(cb, addr, val);
7522 struct elink_dev *cb = params->cb;
7549 ELINK_DEBUG_P3(cb, "port %x, XGXS?%x, int_status 0x%x\n",
7551 REG_RD(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
7553 ELINK_DEBUG_P3(cb, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
7554 REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
7555 REG_RD(cb, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18) > 0,
7556 REG_RD(cb, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
7558 ELINK_DEBUG_P2(cb, " 10G %x, XGXS_LINK %x\n",
7559 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
7560 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
7564 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7582 ELINK_DEBUG_P1(cb, "phy in index %d link is up\n",
7585 ELINK_DEBUG_P1(cb, "phy in index %d link is down\n",
7618 ELINK_DEBUG_P1(cb, "Invalid link indication"
7656 ELINK_DEBUG_P0(cb,
7674 ELINK_DEBUG_P1(cb, "Active external phy selected: %x\n",
7682 elink_rearm_latch_signal(cb, port,
7688 ELINK_DEBUG_P3(cb, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
7699 ELINK_DEBUG_P2(cb, "Internal link speed %d is"
7705 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
7707 MSLEEP(cb, 1);
7724 ELINK_DEBUG_P3(cb, "ext_phy_link_up = %d, int_link_up = %d,"
7769 elink_cb_fw_command(cb, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7780 void elink_ext_phy_hw_reset(struct elink_dev *cb, u8 port)
7782 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1,
7784 MSLEEP(cb, 1);
7785 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1,
7790 static void elink_save_spirom_version(struct elink_dev *cb, u8 port,
7793 ELINK_DEBUG_P3(cb, "FW version 0x%x:0x%x for port %d\n",
7797 REG_WR(cb, ver_addr, spirom_ver);
7801 static void elink_save_bcm_spirom_ver(struct elink_dev *cb,
7807 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD,
7809 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD,
7811 elink_save_spirom_version(cb, port, (u32)(fw_ver1<<16 | fw_ver2),
7817 static void elink_ext_phy_10G_an_resolve(struct elink_dev *cb,
7822 elink_cl45_read(cb, phy,
7825 elink_cl45_read(cb, phy,
7845 struct elink_dev *cb = params->cb;
7857 elink_cl45_read(cb, phy,
7861 elink_cl45_read(cb, phy,
7870 ELINK_DEBUG_P1(cb, "Ext PHY CL37 pause result 0x%x\n",
7876 static elink_status_t elink_8073_8727_external_rom_boot(struct elink_dev *cb,
7886 elink_cl45_write(cb, phy,
7892 elink_cl45_write(cb, phy,
7897 elink_cl45_write(cb, phy,
7902 elink_cl45_write(cb, phy,
7908 elink_cl45_write(cb, phy,
7914 MSLEEP(cb, 100);
7920 ELINK_DEBUG_P2(cb,
7928 elink_cl45_read(cb, phy,
7931 elink_cl45_read(cb, phy,
7935 MSLEEP(cb, 1);
7941 elink_cl45_write(cb, phy,
7944 elink_save_bcm_spirom_ver(cb, phy, port);
7946 ELINK_DEBUG_P2(cb,
7959 static elink_status_t elink_8073_is_snr_needed(struct elink_dev *cb, struct elink_phy *phy)
7965 elink_cl45_read(cb, phy,
7974 elink_cl45_read(cb, phy,
7985 static elink_status_t elink_8073_xaui_wa(struct elink_dev *cb, struct elink_phy *phy)
7989 elink_cl45_read(cb, phy,
8004 elink_cl45_read(cb, phy,
8013 ELINK_DEBUG_P0(cb, "XAUI work-around not required\n");
8016 ELINK_DEBUG_P0(cb, "bit 15 went off\n");
8023 elink_cl45_read(cb, phy,
8027 ELINK_DEBUG_P0(cb,
8031 MSLEEP(cb, 3);
8035 MSLEEP(cb, 3);
8037 ELINK_DEBUG_P0(cb, "Warning: XAUI work-around timeout !!!\n");
8042 static void elink_807x_force_10G(struct elink_dev *cb, struct elink_phy *phy)
8045 elink_cl45_write(cb, phy,
8047 elink_cl45_write(cb, phy,
8049 elink_cl45_write(cb, phy,
8051 elink_cl45_write(cb, phy,
8061 struct elink_dev *cb = params->cb;
8062 elink_cl45_read(cb, phy,
8083 ELINK_DEBUG_P1(cb,
8086 elink_cl45_write(cb, phy,
8089 MSLEEP(cb, 500);
8097 struct elink_dev *cb = params->cb;
8101 elink_cl45_write(cb, phy,
8103 elink_cl45_write(cb, phy,
8113 struct elink_dev *cb = params->cb;
8116 ELINK_DEBUG_P0(cb, "Init 8073\n");
8119 gpio_port = PATH_ID(cb);
8123 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2,
8126 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1,
8132 elink_cl45_read(cb, phy,
8135 elink_cl45_read(cb, phy,
8138 ELINK_DEBUG_P1(cb, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
8143 ELINK_DEBUG_P0(cb, "Swapping polarity for the 8073\n");
8145 elink_cl45_read(cb, phy,
8148 elink_cl45_write(cb, phy,
8156 if (REG_RD(cb, params->shmem_base +
8161 elink_cl45_read(cb, phy,
8164 elink_cl45_write(cb, phy,
8167 ELINK_DEBUG_P0(cb, "Enable CL37 BAM on KR\n");
8171 elink_807x_force_10G(cb, phy);
8172 ELINK_DEBUG_P0(cb, "Forced speed 10G on 807X\n");
8175 elink_cl45_write(cb, phy,
8200 ELINK_DEBUG_P1(cb, "807x autoneg val = 0x%x\n", val);
8203 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
8204 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
8211 elink_cl45_read(cb, phy,
8214 ELINK_DEBUG_P0(cb, "Add 2.5G\n");
8220 ELINK_DEBUG_P0(cb, "Disable 2.5G\n");
8224 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
8227 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
8228 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
8233 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8239 if (elink_8073_is_snr_needed(cb, phy))
8240 elink_cl45_write(cb, phy,
8245 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
8247 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
8252 MSLEEP(cb, 500);
8253 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8254 ELINK_DEBUG_P2(cb, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
8263 struct elink_dev *cb = params->cb;
8269 elink_cl45_read(cb, phy,
8272 ELINK_DEBUG_P1(cb, "8703 LASI status 0x%x\n", val1);
8275 elink_cl45_read(cb, phy,
8277 elink_cl45_read(cb, phy,
8279 ELINK_DEBUG_P2(cb, "807x PCS status 0x%x->0x%x\n", val2, val1);
8281 elink_cl45_read(cb, phy,
8285 elink_cl45_read(cb, phy,
8288 ELINK_DEBUG_P1(cb, "KR 0x9003 0x%x\n", val2);
8291 elink_cl45_read(cb, phy,
8293 ELINK_DEBUG_P1(cb, "KR PCS status 0x%x\n", val2);
8295 elink_cl45_read(cb, phy,
8297 elink_cl45_read(cb, phy,
8300 ELINK_DEBUG_P1(cb, "PMA_REG_STATUS=0x%x\n", val1);
8304 if (elink_8073_xaui_wa(cb, phy) != 0)
8307 elink_cl45_read(cb, phy,
8309 elink_cl45_read(cb, phy,
8313 elink_cl45_read(cb, phy,
8315 elink_cl45_read(cb, phy,
8317 ELINK_DEBUG_P3(cb, "KR PMA status 0x%x->0x%x,"
8321 if (link_up && elink_8073_is_snr_needed(cb, phy)) {
8326 elink_cl45_write(cb, phy,
8331 elink_cl45_write(cb, phy,
8335 elink_cl45_read(cb, phy,
8343 ELINK_DEBUG_P1(cb, "port %x: External link up in 10G\n",
8348 ELINK_DEBUG_P1(cb, "port %x: External link up in 2.5G\n",
8353 ELINK_DEBUG_P1(cb, "port %x: External link up in 1G\n",
8357 ELINK_DEBUG_P1(cb, "port %x: External link is down\n",
8366 elink_cl45_read(cb, phy,
8373 ELINK_DEBUG_P0(cb, "Swapping 1G polarity for"
8379 elink_cl45_write(cb, phy,
8384 elink_ext_phy_10G_an_resolve(cb, phy, vars);
8390 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
8408 struct elink_dev *cb = params->cb;
8411 gpio_port = PATH_ID(cb);
8414 ELINK_DEBUG_P1(cb, "Setting 8073 port %d into low power mode\n",
8416 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2,
8432 struct elink_dev *cb = params->cb;
8433 ELINK_DEBUG_P0(cb, "init 8705\n");
8435 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2,
8438 elink_ext_phy_hw_reset(cb, params->port);
8439 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8440 elink_wait_reset_complete(cb, phy, params);
8442 elink_cl45_write(cb, phy,
8444 elink_cl45_write(cb, phy,
8446 elink_cl45_write(cb, phy,
8448 elink_cl45_write(cb, phy,
8451 elink_save_spirom_version(cb, params->port, params->shmem_base, 0);
8461 struct elink_dev *cb = params->cb;
8462 ELINK_DEBUG_P0(cb, "read status 8705\n");
8463 elink_cl45_read(cb, phy,
8465 ELINK_DEBUG_P1(cb, "8705 LASI status 0x%x\n", val1);
8467 elink_cl45_read(cb, phy,
8469 ELINK_DEBUG_P1(cb, "8705 LASI status 0x%x\n", val1);
8471 elink_cl45_read(cb, phy,
8474 elink_cl45_read(cb, phy,
8476 elink_cl45_read(cb, phy,
8479 ELINK_DEBUG_P1(cb, "8705 1.c809 val=0x%x\n", val1);
8498 struct elink_dev *cb = params->cb;
8505 ELINK_DEBUG_P0(cb, "Disabling PMD transmitter\n");
8507 ELINK_DEBUG_P0(cb, "NOT disabling PMD transmitter\n");
8511 ELINK_DEBUG_P0(cb, "Enabling PMD transmitter\n");
8512 elink_cl45_write(cb, phy,
8523 struct elink_dev *cb = params->cb;
8525 gpio_port = PATH_ID(cb);
8528 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP);
8529 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE);
8539 struct elink_dev *cb = params->cb;
8543 tx_en_mode = REG_RD(cb, params->shmem_base +
8547 ELINK_DEBUG_P3(cb, "Setting transmitter tx_en=%x for port %x "
8552 elink_cl45_read(cb, phy,
8562 elink_cl45_write(cb, phy,
8581 ELINK_SET_GPIO(cb, gpio_pin, gpio_mode, gpio_port);
8585 ELINK_DEBUG_P1(cb, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
8596 struct elink_dev *cb = params->cb;
8597 ELINK_DEBUG_P1(cb, "Setting SFP+ transmitter to %d\n", tx_en);
8617 struct elink_dev *cb = params->cb;
8621 ELINK_DEBUG_P0(cb,
8626 elink_cl45_write(cb, phy,
8631 elink_cl45_write(cb, phy,
8636 elink_cl45_write(cb, phy,
8642 elink_cl45_read(cb, phy,
8648 USLEEP(cb, 5);
8653 ELINK_DEBUG_P1(cb,
8661 elink_cl45_read(cb, phy,
8668 elink_cl45_read(cb, phy,
8674 MSLEEP(cb, 1);
8686 struct elink_dev *cb = params->cb;
8688 pin_cfg = (REG_RD(cb, params->shmem_base +
8696 ELINK_DEBUG_P2(cb, "Setting SFP+ module power to %d using pin cfg %d\n",
8701 elink_set_cfg_pin(cb, pin_cfg, power ^ 1);
8714 struct elink_dev *cb = params->cb;
8717 ELINK_DEBUG_P0(cb,
8728 MSLEEP(cb, 1);
8731 rc = elink_bsc_read(params, cb, dev_addr, addr32, 0, byte_cnt,
8752 struct elink_dev *cb = params->cb;
8756 ELINK_DEBUG_P0(cb,
8765 elink_cl45_write(cb, phy,
8771 elink_cl45_read(cb, phy,
8777 elink_cl45_write(cb, phy,
8783 elink_cl45_write(cb, phy,
8788 elink_cl45_write(cb, phy,
8794 elink_cl45_write(cb, phy,
8801 MSLEEP(cb, 1);
8805 elink_cl45_read(cb, phy,
8811 USLEEP(cb, 5);
8816 ELINK_DEBUG_P1(cb,
8824 elink_cl45_read(cb, phy,
8831 elink_cl45_read(cb, phy,
8837 MSLEEP(cb, 1);
8864 struct elink_dev *cb = params->cb;
8870 ELINK_DEBUG_P1(cb, "invalid dev_addr 0x%x\n", dev_addr);
8915 struct elink_dev *cb = params->cb;
8927 ELINK_DEBUG_P0(cb, "Failed to read from SFP+ module EEPROM\n");
8947 ELINK_DEBUG_P0(cb, "Active Copper cable detected\n");
8960 ELINK_DEBUG_P0(cb,
8963 ELINK_DEBUG_P0(cb,
8980 ELINK_DEBUG_P0(cb, "1G SFP module detected\n");
8989 gport = PATH_ID(cb) +
8992 elink_cb_event_log(cb, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
9005 MSLEEP(cb, 40);
9010 ELINK_DEBUG_P0(cb, "10G Optic module detected\n");
9022 ELINK_DEBUG_P1(cb, "Unable to determine module type 0x%x !!!\n",
9029 media_types = REG_RD(cb, sync_offset);
9041 REG_WR(cb, sync_offset, media_types);
9050 ELINK_DEBUG_P0(cb,
9059 ELINK_DEBUG_P1(cb, "EDC mode is set to 0x%x\n", *edc_mode);
9069 struct elink_dev *cb = params->cb;
9075 val = REG_RD(cb, params->shmem_base +
9080 ELINK_DEBUG_P0(cb, "NOT enforcing module verification\n");
9092 ELINK_DEBUG_P0(cb,
9099 ELINK_DEBUG_P0(cb,
9105 fw_resp = elink_cb_fw_command(cb, cmd, fw_cmd_param);
9107 ELINK_DEBUG_P0(cb, "Approved module\n");
9131 elink_cb_event_log(cb, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
9148 struct elink_dev *cb = params->cb;
9166 ELINK_DEBUG_P1(cb,
9171 MSLEEP(cb, 5);
9181 static void elink_8727_power_module(struct elink_dev *cb,
9207 elink_cl45_write(cb, phy,
9215 static elink_status_t elink_8726_set_limiting_mode(struct elink_dev *cb,
9221 elink_cl45_read(cb, phy,
9225 ELINK_DEBUG_P1(cb, "Current Limiting mode is 0x%x\n",
9229 ELINK_DEBUG_P0(cb, "Setting LIMITING MODE\n");
9230 elink_cl45_write(cb, phy,
9236 ELINK_DEBUG_P0(cb, "Setting LRM MODE\n");
9244 elink_cl45_write(cb, phy,
9248 elink_cl45_write(cb, phy,
9252 elink_cl45_write(cb, phy,
9256 elink_cl45_write(cb, phy,
9266 static elink_status_t elink_8727_set_limiting_mode(struct elink_dev *cb,
9272 elink_cl45_read(cb, phy,
9277 elink_cl45_write(cb, phy,
9282 elink_cl45_read(cb, phy,
9287 elink_cl45_write(cb, phy,
9292 elink_cl45_write(cb, phy,
9304 struct elink_dev *cb = params->cb;
9315 elink_cl45_write(cb, phy,
9318 elink_cl45_write(cb, phy,
9321 elink_cl45_write(cb, phy,
9324 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD,
9335 elink_cl45_write(cb, phy,
9340 ELINK_DEBUG_P1(cb, "Function 0x%x not supported by 8727\n",
9350 struct elink_dev *cb = params->cb;
9352 u32 fault_led_gpio = REG_RD(cb, params->shmem_base +
9367 ELINK_DEBUG_P3(cb, "Set fault module-detected led "
9370 ELINK_SET_GPIO(cb, gpio_pin, gpio_mode, gpio_port);
9374 ELINK_DEBUG_P1(cb, "Error: Invalid fault led mode 0x%x\n",
9388 struct elink_dev *cb = params->cb;
9389 pin_cfg = (REG_RD(cb, params->shmem_base +
9394 ELINK_DEBUG_P2(cb, "Setting Fault LED to %d using pin cfg %d\n",
9396 elink_set_cfg_pin(cb, pin_cfg, gpio_mode);
9402 struct elink_dev *cb = params->cb;
9403 ELINK_DEBUG_P1(cb, "Setting SFP+ module fault LED to %d\n", gpio_mode);
9419 struct elink_dev *cb = params->cb;
9422 REG_WR(cb, MISC_REG_WC0_RESET, 0x0c0e);
9425 REG_WR(cb, MISC_REG_LCPLL_E40_PWRDWN, 1);
9426 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
9427 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
9438 struct elink_dev *cb = params->cb;
9440 ELINK_DEBUG_P1(cb, "Setting SFP+ power to %x\n", power);
9446 elink_8727_power_module(params->cb, phy, power);
9465 struct elink_dev *cb = params->cb;
9469 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
9487 elink_cl45_write(cb, phy, MDIO_WC_DEVAD,
9490 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
9494 elink_warpcore_reset_lane(cb, phy, 1);
9495 elink_warpcore_reset_lane(cb, phy, 0);
9507 elink_8726_set_limiting_mode(params->cb, phy, edc_mode);
9513 elink_8727_set_limiting_mode(params->cb, phy, edc_mode);
9527 struct elink_dev *cb = params->cb;
9531 u32 val = REG_RD(cb, params->shmem_base +
9536 ELINK_DEBUG_P1(cb, "SFP+ module plugged in/out detected on port %d\n",
9541 ELINK_DEBUG_P0(cb, "Failed to get valid module type\n");
9546 ELINK_DEBUG_P0(cb, "Module verification failed!!\n");
9555 ELINK_DEBUG_P0(cb, "Shutdown SFP+ module!!\n");
9585 struct elink_dev *cb = params->cb;
9596 if (elink_get_mod_abs_int_cfg(cb, params->chip_id, params->shmem_base,
9599 ELINK_DEBUG_P0(cb, "Failed to get MOD_ABS interrupt config\n");
9607 gpio_val = ELINK_GET_GPIO(cb, gpio_num, gpio_port);
9614 elink_set_mdio_emac_per_phy(cb, params);
9618 ELINK_SET_GPIO_INT(cb, gpio_num,
9629 elink_cl45_read(cb, phy,
9636 elink_warpcore_reset_lane(cb, phy, 1);
9638 elink_warpcore_reset_lane(cb, phy, 0);
9642 ELINK_DEBUG_P0(cb, "SFP+ module is not initialized\n");
9648 ELINK_SET_GPIO_INT(cb, gpio_num,
9664 static void elink_sfp_mask_fault(struct elink_dev *cb,
9670 elink_cl45_read(cb, phy,
9673 elink_cl45_read(cb, phy,
9677 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
9682 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
9695 struct elink_dev *cb = params->cb;
9696 ELINK_DEBUG_P0(cb, "XGXS 8706/8726\n");
9698 elink_cl45_read(cb, phy,
9701 elink_sfp_mask_fault(cb, phy, MDIO_PMA_LASI_TXSTAT,
9705 elink_cl45_read(cb, phy,
9707 elink_cl45_read(cb, phy,
9709 ELINK_DEBUG_P2(cb, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
9711 elink_cl45_read(cb, phy,
9713 elink_cl45_read(cb, phy,
9715 elink_cl45_read(cb, phy,
9717 elink_cl45_read(cb, phy,
9720 ELINK_DEBUG_P3(cb, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
9737 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD,
9739 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD,
9757 struct elink_dev *cb = params->cb;
9759 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2,
9762 elink_ext_phy_hw_reset(cb, params->port);
9763 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
9764 elink_wait_reset_complete(cb, phy, params);
9768 elink_cl45_read(cb, phy,
9772 MSLEEP(cb, 10);
9774 ELINK_DEBUG_P1(cb, "XGXS 8706 is initialized after %d ms\n", cnt);
9783 elink_cl45_read(cb, phy, MDIO_XS_DEVAD, reg, &val);
9788 ELINK_DEBUG_P2(cb, "Setting RX Equalizer to BCM8706"
9790 elink_cl45_write(cb, phy, MDIO_XS_DEVAD, reg, val);
9795 ELINK_DEBUG_P0(cb, "XGXS 8706 force 10Gbps\n");
9797 elink_cl45_write(cb, phy,
9800 elink_cl45_write(cb, phy,
9804 elink_cl45_write(cb, phy,
9810 ELINK_DEBUG_P0(cb, "XGXS 8706 AutoNeg\n");
9811 elink_cl45_write(cb, phy,
9815 elink_cl45_write(cb, phy,
9818 elink_cl45_write(cb, phy,
9821 elink_cl45_write(cb, phy,
9825 elink_cl45_write(cb, phy,
9827 elink_cl45_write(cb, phy,
9830 elink_cl45_write(cb, phy,
9834 elink_save_bcm_spirom_ver(cb, phy, params->port);
9840 tx_en_mode = REG_RD(cb, params->shmem_base +
9846 ELINK_DEBUG_P0(cb, "Enabling TXONOFF_PWRDN_DIS\n");
9847 elink_cl45_read(cb, phy,
9850 elink_cl45_write(cb, phy,
9870 struct elink_dev *cb = params->cb;
9871 ELINK_DEBUG_P0(cb, "PMA/PMD ext_phy_loopback: 8726\n");
9872 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9878 struct elink_dev *cb = params->cb;
9880 MSLEEP(cb, 100);
9883 elink_cl45_write(cb, phy,
9887 elink_cl45_write(cb, phy,
9892 elink_cl45_write(cb, phy,
9896 elink_cl45_write(cb, phy,
9902 MSLEEP(cb, 150);
9905 elink_cl45_write(cb, phy,
9909 MSLEEP(cb, 200);
9910 elink_save_bcm_spirom_ver(cb, phy, params->port);
9917 struct elink_dev *cb = params->cb;
9921 elink_cl45_read(cb, phy,
9925 ELINK_DEBUG_P0(cb, "Tx is disabled\n");
9938 struct elink_dev *cb = params->cb;
9939 ELINK_DEBUG_P0(cb, "Initializing BCM8726\n");
9941 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9942 elink_wait_reset_complete(cb, phy, params);
9954 ELINK_DEBUG_P0(cb, "Setting 1G force\n");
9955 elink_cl45_write(cb, phy,
9957 elink_cl45_write(cb, phy,
9959 elink_cl45_write(cb, phy,
9961 elink_cl45_write(cb, phy,
9970 ELINK_DEBUG_P0(cb, "Setting 1G clause37\n");
9973 elink_cl45_write(cb, phy,
9975 elink_cl45_write(cb, phy,
9977 elink_cl45_write(cb, phy,
9979 elink_cl45_write(cb, phy,
9981 elink_cl45_write(cb, phy,
9986 elink_cl45_write(cb, phy,
9988 elink_cl45_write(cb, phy,
9993 elink_cl45_write(cb, phy,
10000 ELINK_DEBUG_P2(cb,
10004 elink_cl45_write(cb, phy,
10009 elink_cl45_write(cb, phy,
10023 struct elink_dev *cb = params->cb;
10024 ELINK_DEBUG_P1(cb, "elink_8726_link_reset port %d\n", params->port);
10026 elink_cl45_write(cb, phy,
10041 struct elink_dev *cb = params->cb;
10063 elink_cl45_read(cb, phy,
10069 elink_cl45_write(cb, phy,
10073 elink_cl45_read(cb, phy,
10079 elink_cl45_write(cb, phy,
10091 struct elink_dev *cb = params->cb;
10092 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP);
10093 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE);
10095 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1,
10102 struct elink_dev *cb = params->cb;
10107 ELINK_DEBUG_P0(cb, "Setting 1G force\n");
10108 elink_cl45_write(cb, phy,
10110 elink_cl45_write(cb, phy,
10112 elink_cl45_read(cb, phy,
10114 ELINK_DEBUG_P1(cb, "1.7 = 0x%x\n", tmp1);
10119 elink_cl45_read(cb, phy,
10123 elink_cl45_write(cb, phy,
10134 ELINK_DEBUG_P0(cb, "Setting 1G clause37\n");
10135 elink_cl45_write(cb, phy,
10137 elink_cl45_write(cb, phy,
10143 elink_cl45_write(cb, phy,
10146 elink_cl45_write(cb, phy,
10148 elink_cl45_write(cb, phy,
10150 elink_cl45_write(cb, phy,
10162 struct elink_dev *cb = params->cb;
10165 elink_wait_reset_complete(cb, phy, params);
10167 ELINK_DEBUG_P0(cb, "Initializing BCM8727\n");
10173 elink_cl45_read(cb, phy,
10182 elink_cl45_write(cb, phy,
10188 elink_8727_power_module(cb, phy, 1);
10190 elink_cl45_read(cb, phy,
10193 elink_cl45_read(cb, phy,
10202 ELINK_DEBUG_P2(cb, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
10205 elink_cl45_write(cb, phy,
10209 elink_cl45_write(cb, phy,
10217 tx_en_mode = REG_RD(cb, params->shmem_base +
10224 ELINK_DEBUG_P0(cb, "Enabling TXONOFF_PWRDN_DIS\n");
10225 elink_cl45_read(cb, phy,
10229 elink_cl45_write(cb, phy,
10231 elink_cl45_read(cb, phy,
10234 elink_cl45_write(cb, phy,
10245 struct elink_dev *cb = params->cb;
10247 u32 val = REG_RD(cb, params->shmem_base +
10251 elink_cl45_read(cb, phy,
10257 ELINK_DEBUG_P0(cb,
10270 elink_cl45_write(cb, phy,
10277 elink_cl45_read(cb, phy,
10283 ELINK_DEBUG_P0(cb,
10295 elink_cl45_write(cb, phy,
10304 elink_cl45_read(cb, phy,
10316 ELINK_DEBUG_P0(cb, "SFP+ module is not initialized\n");
10322 ELINK_DEBUG_P1(cb, "8727 RX_ALARM_STATUS 0x%x\n",
10332 struct elink_dev *cb = params->cb;
10338 elink_cl45_read(cb, phy,
10345 elink_cl45_read(cb, phy,
10349 ELINK_DEBUG_P1(cb, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
10351 elink_sfp_mask_fault(cb, phy, MDIO_PMA_LASI_TXSTAT,
10354 elink_cl45_read(cb, phy,
10357 ELINK_DEBUG_P1(cb, "8727 LASI status 0x%x\n", val1);
10360 elink_cl45_read(cb, phy,
10368 elink_cl45_read(cb, phy,
10376 oc_port = PATH_ID(cb) + (params->port << 1);
10377 ELINK_DEBUG_P1(cb,
10380 elink_cb_event_log(cb, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
10389 elink_cl45_write(cb, phy,
10393 elink_cl45_read(cb, phy,
10398 elink_cl45_write(cb, phy,
10402 elink_cl45_read(cb, phy,
10405 elink_8727_power_module(params->cb, phy, 0);
10414 elink_cl45_write(cb, phy,
10420 ELINK_DEBUG_P0(cb, "Enabling 8727 TX laser\n");
10423 ELINK_DEBUG_P0(cb, "Tx is disabled\n");
10427 elink_cl45_read(cb, phy,
10437 ELINK_DEBUG_P1(cb, "port %x: External link up in 10G\n",
10442 ELINK_DEBUG_P1(cb, "port %x: External link up in 1G\n",
10446 ELINK_DEBUG_P1(cb, "port %x: External link is down\n",
10452 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD,
10455 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD,
10466 ELINK_DEBUG_P1(cb, "duplex = 0x%x\n", vars->duplex);
10471 elink_cl45_read(cb, phy,
10481 elink_cl45_write(cb, phy,
10492 struct elink_dev *cb = params->cb;
10500 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
10512 struct elink_dev *cb,
10529 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
10530 elink_save_spirom_version(cb, port, fw_ver1 & 0xfff,
10537 elink_cl45_write(cb, phy, reg_set[i].devad,
10541 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10544 USLEEP(cb, 5);
10547 ELINK_DEBUG_P0(cb, "Unable to read 848xx "
10549 elink_save_spirom_version(cb, port, 0,
10556 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
10557 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
10558 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
10560 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10563 USLEEP(cb, 5);
10566 ELINK_DEBUG_P0(cb, "Unable to read 848xx phy fw "
10568 elink_save_spirom_version(cb, port, 0,
10574 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
10576 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
10578 elink_save_spirom_version(cb, port, (fw_ver2<<16) | fw_ver1,
10585 static void elink_848xx_set_led(struct elink_dev *cb,
10599 elink_cl45_read(cb, phy,
10605 elink_cl45_write(cb, phy,
10610 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg,
10620 elink_cl45_read_or_write(cb, phy,
10629 struct elink_dev *cb = params->cb;
10635 elink_save_848xx_spirom_version(phy, cb, params->port);
10641 elink_bits_en(cb, NIG_REG_LATCH_BC_0 + params->port*4,
10644 elink_848xx_set_led(cb, phy);
10653 struct elink_dev *cb = params->cb;
10657 elink_cl45_write(cb, phy,
10661 elink_cl45_read(cb, phy,
10666 elink_cl45_read(cb, phy,
10670 elink_cl45_read(cb, phy,
10685 ELINK_DEBUG_P0(cb, "Advertising 1G\n");
10689 elink_cl45_write(cb, phy,
10701 ELINK_DEBUG_P0(cb, "Advertising 100M-FD\n");
10710 ELINK_DEBUG_P0(cb, "Advertising 100M-HD\n");
10718 ELINK_DEBUG_P0(cb, "Advertising 10M-FD\n");
10726 ELINK_DEBUG_P0(cb, "Advertising 10M-HD\n");
10737 elink_cl45_write(cb, phy,
10742 ELINK_DEBUG_P0(cb, "Setting 100M force\n");
10749 elink_cl45_write(cb, phy,
10752 ELINK_DEBUG_P0(cb, "Setting 10M force\n");
10755 elink_cl45_write(cb, phy,
10768 elink_cl45_write(cb, phy,
10776 ELINK_DEBUG_P0(cb, "Advertising 10G\n");
10780 cb, phy,
10784 elink_cl45_write(cb, phy,
10788 elink_cl45_write(cb, phy,
10804 struct elink_dev *cb = params->cb;
10806 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2,
10810 elink_ext_phy_hw_reset(cb, params->port);
10811 elink_wait_reset_complete(cb, phy, params);
10813 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
10828 struct elink_dev *cb = params->cb;
10830 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD,
10834 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD,
10838 MSLEEP(cb, 1);
10841 ELINK_DEBUG_P0(cb, "FW cmd: FW not ready.\n");
10847 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD,
10851 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD,
10854 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD,
10859 MSLEEP(cb, 1);
10863 ELINK_DEBUG_P0(cb, "FW cmd failed.\n");
10868 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD,
10872 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD,
10886 struct elink_dev *cb = params->cb;
10889 pair_swap = REG_RD(cb, params->shmem_base +
10903 ELINK_DEBUG_P1(cb, "Pairswap OK, val=0x%x\n", data[1]);
10909 static u8 elink_84833_get_reset_gpios(struct elink_dev *cb,
10920 reset_pin[idx] = REG_RD(cb, shmem_base_path[idx] +
10933 reset_pin[idx] = REG_RD(cb, shmem_base_path[idx] +
10951 struct elink_dev *cb = params->cb;
10953 u32 other_shmem_base_addr = REG_RD(cb, params->shmem2_base +
10960 elink_cl45_write(cb, phy, MDIO_AN_DEVAD,
10963 elink_cl45_write(cb, phy, MDIO_AN_DEVAD,
10970 reset_gpios = elink_84833_get_reset_gpios(cb, shmem_base_path,
10974 ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10975 USLEEP(cb, 10);
10976 ELINK_DEBUG_P1(cb, "84833 hw reset on pin values 0x%x\n",
10993 struct elink_dev *cb = params->cb;
10997 ELINK_DEBUG_P0(cb, "Don't Advertise 10GBase-T EEE\n");
11003 ELINK_DEBUG_P0(cb, "EEE disable failed.\n");
11016 struct elink_dev *cb = params->cb;
11023 ELINK_DEBUG_P0(cb, "EEE enable failed.\n");
11037 struct elink_dev *cb = params->cb;
11046 MSLEEP(cb, 1);
11049 port = PATH_ID(cb);
11054 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_3,
11059 elink_cl45_write(cb, phy,
11064 elink_wait_reset_complete(cb, phy, params);
11067 MSLEEP(cb, 50);
11087 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD,
11126 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD,
11128 ELINK_DEBUG_P2(cb, "Multi_phy config = 0x%x, Media control = 0x%x\n",
11145 ELINK_DEBUG_P0(cb, "Cfg AutogrEEEn failed.\n");
11152 elink_save_848xx_spirom_version(phy, cb, params->port);
11157 u32 cms_enable = REG_RD(cb, params->shmem_base +
11162 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD,
11168 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD,
11174 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD,
11183 ELINK_DEBUG_P0(cb, "Failed to configure EEE timers\n");
11196 ELINK_DEBUG_P0(cb, "Failed to set EEE advertisement\n");
11208 elink_cl45_read_and_write(cb, phy,
11221 struct elink_dev *cb = params->cb;
11228 elink_cl45_read(cb, phy,
11230 elink_cl45_read(cb, phy,
11233 ELINK_DEBUG_P1(cb, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
11240 elink_ext_phy_10G_an_resolve(cb, phy, vars);
11245 elink_cl45_write(cb, phy,
11250 elink_cl45_read(cb, phy,
11255 ELINK_DEBUG_P1(cb, "Legacy speed status = 0x%x\n",
11275 elink_cl45_read(cb, phy,
11290 ELINK_DEBUG_P2(cb,
11295 elink_cl45_read(cb, phy,
11302 elink_cl45_read(cb, phy,
11312 ELINK_DEBUG_P1(cb, "BCM848x3: link speed is %d\n",
11317 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
11335 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
11345 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
11378 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1,
11380 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1,
11388 elink_cl45_write(params->cb, phy,
11390 elink_cl45_write(params->cb, phy,
11399 struct elink_dev *cb = params->cb;
11404 port = PATH_ID(cb);
11409 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_3,
11413 elink_cl45_read(cb, phy,
11417 elink_cl45_write(cb, phy,
11426 struct elink_dev *cb = params->cb;
11432 port = PATH_ID(cb);
11439 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE OFF\n", port);
11445 elink_cl45_write(cb, phy,
11450 elink_cl45_write(cb, phy,
11455 elink_cl45_write(cb, phy,
11460 elink_cl45_write(cb, phy,
11466 elink_cl45_write(cb, phy,
11474 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
11481 elink_cl45_write(cb, phy,
11486 elink_cl45_write(cb, phy,
11491 elink_cl45_write(cb, phy,
11496 elink_cl45_write(cb, phy,
11502 elink_cl45_write(cb, phy,
11511 if (REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 +
11518 cb,
11523 elink_cl45_write(cb, phy,
11532 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE ON\n", port);
11537 elink_cl45_read(cb, phy,
11544 elink_cl45_write(cb, phy,
11550 elink_cl45_write(cb, phy,
11555 elink_cl45_write(cb, phy,
11560 elink_cl45_write(cb, phy,
11565 elink_cl45_write(cb, phy,
11570 elink_cl45_write(cb, phy,
11579 if (REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 +
11586 cb,
11591 elink_cl45_write(cb, phy,
11601 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE OPER\n", port);
11607 elink_cl45_read(cb, phy,
11615 ELINK_DEBUG_P0(cb, "Setting LINK_SIGNAL\n");
11616 elink_cl45_write(cb, phy,
11623 elink_cl45_write(cb, phy,
11628 elink_cl45_write(cb, phy,
11633 elink_cl45_write(cb, phy,
11638 elink_cl45_write(cb, phy,
11652 elink_cl45_write(cb, phy,
11658 elink_cl45_read(cb, phy,
11664 elink_cl45_write(cb, phy,
11673 elink_cl45_write(cb, phy,
11692 elink_cl45_read(cb, phy, MDIO_WC_DEVAD,
11708 struct elink_dev *cb = params->cb;
11710 elink_cl22_read(cb, phy,
11716 elink_cl22_read(cb, phy,
11719 elink_cl22_read(cb, phy,
11722 elink_cl22_read(cb, phy,
11725 elink_cl22_read(cb, phy,
11743 struct elink_dev *cb = params->cb;
11749 elink_cl22_write(cb, phy,
11752 elink_cl22_read(cb, phy,
11757 elink_cl22_write(cb, phy,
11761 elink_cl22_write(cb, phy,
11772 struct elink_dev *cb = params->cb;
11783 ELINK_DEBUG_P0(cb, "54618SE cfg init\n");
11784 MSLEEP(cb, 1);
11791 cfg_pin = (REG_RD(cb, params->shmem_base +
11798 elink_set_cfg_pin(cb, cfg_pin, 1);
11801 MSLEEP(cb, 50);
11804 elink_cl22_write(cb, phy,
11806 elink_wait_reset_complete(cb, phy, params);
11809 MSLEEP(cb, 50);
11817 elink_cl22_write(cb, phy,
11820 elink_cl22_read(cb, phy,
11824 elink_cl22_write(cb, phy,
11845 elink_cl22_read(cb, phy,
11849 elink_cl22_read(cb, phy,
11853 elink_cl22_read(cb, phy,
11870 ELINK_DEBUG_P0(cb, "Advertising 1G\n");
11874 elink_cl22_write(cb, phy,
11877 elink_cl22_read(cb, phy,
11887 ELINK_DEBUG_P0(cb, "Advertising 10M-HD\n");
11893 ELINK_DEBUG_P0(cb, "Advertising 10M-FD\n");
11899 ELINK_DEBUG_P0(cb, "Advertising 100M-HD\n");
11905 ELINK_DEBUG_P0(cb, "Advertising 100M-FD\n");
11913 elink_cl22_write(cb, phy,
11916 ELINK_DEBUG_P0(cb, "Setting 100M force\n");
11920 elink_cl22_write(cb, phy,
11923 ELINK_DEBUG_P0(cb, "Setting 10M force\n");
11929 elink_cl22_write(cb, phy, MDIO_REG_GPHY_EXP_ACCESS,
11932 elink_cl22_read(cb, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
11934 elink_cl22_write(cb, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
11938 ELINK_DEBUG_P0(cb, "Failed to configure EEE timers\n");
11952 ELINK_DEBUG_P0(cb, "Don't Advertise 1GBase-T EEE\n");
11964 ELINK_DEBUG_P0(cb, "Enabling Auto-GrEEEn\n");
11967 ELINK_DEBUG_P0(cb, "Don't Adv. EEE\n");
11969 elink_cl45_write(cb, phy, MDIO_AN_DEVAD,
11974 elink_cl22_write(cb, phy,
11981 elink_cl22_write(cb, phy,
11992 struct elink_dev *cb = params->cb;
11995 elink_cl22_write(cb, phy,
11998 elink_cl22_read(cb, phy,
12003 ELINK_DEBUG_P1(cb, "54618x set link led (mode=%x)\n", mode);
12018 elink_cl22_write(cb, phy,
12029 struct elink_dev *cb = params->cb;
12040 elink_cl22_write(cb, phy, MDIO_PMA_REG_CTRL, 0x800);
12045 cfg_pin = (REG_RD(cb, params->shmem_base +
12052 elink_set_cfg_pin(cb, cfg_pin, 0);
12059 struct elink_dev *cb = params->cb;
12065 elink_cl22_read(cb, phy,
12068 ELINK_DEBUG_P1(cb, "54618SE read_status: 0x%x\n", legacy_status);
12071 elink_cl22_read(cb, phy,
12102 ELINK_DEBUG_P2(cb,
12108 elink_cl22_read(cb, phy,
12114 elink_cl22_read(cb, phy,
12121 ELINK_DEBUG_P1(cb, "BCM54618SE: link speed is %d\n",
12128 elink_cl22_read(cb, phy, 0x5, &val);
12146 elink_cl22_read(cb, phy, 0xa, &val);
12166 struct elink_dev *cb = params->cb;
12170 ELINK_DEBUG_P0(cb, "2PMA/PMD ext_phy_loopback: 54618se\n");
12174 elink_cl22_write(cb, phy, 0x09, 3<<11);
12181 elink_cl22_read(cb, phy, 0x00, &val);
12184 elink_cl22_write(cb, phy, 0x00, val);
12190 elink_cl22_write(cb, phy, 0x18, 7);
12191 elink_cl22_read(cb, phy, 0x18, &val);
12192 elink_cl22_write(cb, phy, 0x18, val | (1<<10) | (1<<15));
12195 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
12200 REG_WR(cb, umac_base + UMAC_REG_MAXFR, 0x2710);
12212 struct elink_dev *cb = params->cb;
12214 elink_cl45_write(cb, phy,
12223 struct elink_dev *cb = params->cb;
12224 ELINK_DEBUG_P0(cb, "Setting the SFX7101 LASI indication\n");
12227 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2,
12230 elink_ext_phy_hw_reset(cb, params->port);
12231 elink_wait_reset_complete(cb, phy, params);
12233 elink_cl45_write(cb, phy,
12235 ELINK_DEBUG_P0(cb, "Setting the SFX7101 LED to blink on traffic\n");
12236 elink_cl45_write(cb, phy,
12241 elink_cl45_read(cb, phy,
12244 elink_cl45_write(cb, phy,
12248 elink_cl45_read(cb, phy,
12251 elink_cl45_read(cb, phy,
12253 elink_save_spirom_version(cb, params->port,
12262 struct elink_dev *cb = params->cb;
12265 elink_cl45_read(cb, phy,
12267 elink_cl45_read(cb, phy,
12269 ELINK_DEBUG_P2(cb, "10G-base-T LASI status 0x%x->0x%x\n",
12271 elink_cl45_read(cb, phy,
12273 elink_cl45_read(cb, phy,
12275 ELINK_DEBUG_P2(cb, "10G-base-T PMA status 0x%x->0x%x\n",
12280 elink_cl45_read(cb, phy,
12285 ELINK_DEBUG_P2(cb, "SFX7101 AN status 0x%x->Master=%x\n",
12287 elink_ext_phy_10G_an_resolve(cb, phy, vars);
12311 void elink_sfx7101_sp_sw_reset(struct elink_dev *cb, struct elink_phy *phy)
12315 elink_cl45_read(cb, phy,
12320 MSLEEP(cb, 50);
12322 elink_cl45_write(cb, phy,
12327 elink_cl45_read(cb, phy,
12340 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_2,
12343 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1,
12352 struct elink_dev *cb = params->cb;
12365 elink_cl45_write(cb, phy,
12916 static void elink_populate_preemphasis(struct elink_dev *cb, u32 shmem_base,
12928 rx = REG_RD(cb, shmem_base +
12932 tx = REG_RD(cb, shmem_base +
12936 rx = REG_RD(cb, shmem_base +
12940 tx = REG_RD(cb, shmem_base +
12954 static u32 elink_get_ext_phy_config(struct elink_dev *cb, u32 shmem_base,
12960 ext_phy_config = REG_RD(cb, shmem_base +
12965 ext_phy_config = REG_RD(cb, shmem_base +
12970 ELINK_DEBUG_P1(cb, "Invalid phy_index %d\n", phy_index);
12977 static elink_status_t elink_populate_int_phy(struct elink_dev *cb, u32 shmem_base, u8 port,
12982 u32 switch_cfg = (REG_RD(cb, shmem_base +
12986 chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) |
12987 ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12);
12989 ELINK_DEBUG_P1(cb, ":chip_id = 0x%x\n", chip_id);
12993 phy_addr = REG_RD(cb,
12996 if (REG_RD(cb, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
13001 serdes_net_if = (REG_RD(cb, shmem_base +
13067 ELINK_DEBUG_P1(cb, "Unknown WC interface type 0x%x\n",
13086 phy_addr = REG_RD(cb,
13094 phy_addr = REG_RD(cb,
13101 ELINK_DEBUG_P0(cb, "Invalid switch_cfg\n");
13106 phy->mdio_ctrl = elink_get_emac_base(cb,
13114 ELINK_DEBUG_P3(cb, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
13117 elink_populate_preemphasis(cb, shmem_base, phy, port, ELINK_INT_PHY);
13122 static elink_status_t elink_populate_ext_phy(struct elink_dev *cb,
13131 ext_phy_config = elink_get_ext_phy_config(cb, shmem_base,
13211 elink_populate_preemphasis(cb, shmem_base, phy, port, phy_index);
13217 config2 = REG_RD(cb, shmem_base + OFFSETOF(struct shmem_region,
13228 u32 size = REG_RD(cb, shmem2_base);
13243 phy->mdio_ctrl = elink_get_emac_base(cb, mdc_mdio_access, port);
13251 u32 raw_ver = REG_RD(cb, phy->ver_addr);
13258 ELINK_DEBUG_P3(cb, "phy_type 0x%x port %d found in index %d\n",
13260 ELINK_DEBUG_P2(cb, " addr=0x%x, mdio_ctl=0x%x\n",
13266 static elink_status_t elink_populate_phy(struct elink_dev *cb, u8 phy_index, u32 shmem_base,
13272 return elink_populate_int_phy(cb, shmem_base, port, phy);
13274 status = elink_populate_ext_phy(cb, phy_index, shmem_base, shmem2_base,
13284 struct elink_dev *cb = params->cb;
13288 link_config = REG_RD(cb, params->shmem_base +
13291 phy->speed_cap_mask = REG_RD(cb, params->shmem_base +
13296 link_config = REG_RD(cb, params->shmem_base +
13299 phy->speed_cap_mask = REG_RD(cb, params->shmem_base +
13304 ELINK_DEBUG_P3(cb,
13391 struct elink_dev *cb = params->cb;
13394 ELINK_DEBUG_P0(cb, "Begin phy probe\n");
13411 ELINK_DEBUG_P3(cb, "phy_config_swapped %x, phy_index %x,"
13415 if (elink_populate_phy(cb, phy_index, params->shmem_base,
13419 ELINK_DEBUG_P1(cb, "phy probe failed in phy index %d\n",
13441 media_types = REG_RD(cb, sync_offset);
13455 REG_WR(cb, sync_offset, media_types);
13461 ELINK_DEBUG_P1(cb, "End phy probe. #phys found %x\n", params->num_phys);
13488 struct elink_dev *cb = params->cb;
13495 else if (elink_is_4_port_mode(cb))
13503 ELINK_DEBUG_P1(cb, "Invalid line speed %d while UMAC is"
13521 ELINK_DEBUG_P1(cb, "Invalid line speed %d for UMAC\n",
13535 ELINK_DEBUG_P1(cb, "Invalid line speed %d while XMAC is"
13548 ELINK_DEBUG_P1(cb, "Invalid line speed %d for XMAC\n",
13564 struct elink_dev *cb = params->cb;
13601 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13613 struct elink_dev *cb = params->cb;
13640 ELINK_DEBUG_P1(cb, "Invalid link speed %d\n",
13665 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13676 struct elink_dev *cb = params->cb;
13690 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13696 struct elink_dev *cb = params->cb;
13709 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13715 struct elink_dev *cb = params->cb;
13729 elink_warpcore_reset_lane(cb, ¶ms->phy[0], 0);
13735 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13741 struct elink_dev *cb = params->cb;
13750 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13756 struct elink_dev *cb = params->cb;
13800 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13809 struct elink_dev *cb = params->cb;
13815 REG_WR(cb, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
13818 REG_WR(cb, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
13822 REG_WR(cb, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
13832 struct elink_dev *cb = params->cb;
13834 elink_set_mdio_emac_per_phy(cb, params);
13846 ELINK_DEBUG_P0(cb, "Calling PHY specific func\n");
13856 lfa_sts = REG_RD(cb, params->lfa_base +
13866 REG_WR(cb, GRCBASE_MISC +
13870 REG_WR(cb, GRCBASE_MISC +
13897 REG_WR(cb, params->lfa_base +
13901 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13913 struct elink_dev *cb = params->cb;
13920 REG_WR(cb, params->lfa_base +
13924 REG_WR(cb, params->lfa_base +
13928 REG_WR(cb, params->lfa_base +
13933 REG_WR(cb, params->lfa_base +
13939 tmp_val = REG_RD(cb, params->lfa_base +
13944 REG_WR(cb, params->lfa_base +
13947 lfa_sts = REG_RD(cb, params->lfa_base +
13963 REG_WR(cb, params->lfa_base +
13971 struct elink_dev *cb = params->cb;
13972 ELINK_DEBUG_P0(cb, "Phy Initialization started\n");
13973 ELINK_DEBUG_P2(cb, "(1) req_speed %d, req_flowctrl %d\n",
13975 ELINK_DEBUG_P2(cb, "(2) req_speed %d, req_flowctrl %d\n",
13977 ELINK_DEBUG_P1(cb, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
13997 ELINK_DEBUG_P0(cb, "Link Flap Avoidance in progress\n");
14001 ELINK_DEBUG_P1(cb, "Cannot avoid link flap lfa_sta=0x%x\n",
14006 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
14023 ELINK_DEBUG_P0(cb, "No phy found for initialization !!\n");
14028 ELINK_DEBUG_P1(cb, "Num of phys on board: %d\n", params->num_phys);
14065 elink_serdes_deassert(cb, params->port);
14070 MSLEEP(cb, 30);
14088 struct elink_dev *cb = params->cb;
14090 ELINK_DEBUG_P1(cb, "Resetting the link of port %d\n", port);
14100 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
14107 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
14111 REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0);
14112 REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
14122 elink_set_bmac_rx(cb, params->chip_id, port, 0);
14138 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0);
14140 MSLEEP(cb, 10);
14145 elink_set_mdio_emac_per_phy(cb, params);
14166 elink_rearm_latch_signal(cb, port, 0);
14167 elink_bits_dis(cb, NIG_REG_LATCH_BC_0 + port*4,
14180 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
14182 REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0);
14183 REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0);
14188 if (REG_RD(cb, MISC_REG_RESET_REG_2) &
14190 REG_WR(cb, xmac_base + XMAC_REG_CTRL,
14203 struct elink_dev *cb = params->cb;
14213 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
14220 elink_set_bmac_rx(cb, params->chip_id, params->port, 0);
14227 MSLEEP(cb, 10);
14243 elink_set_bmac_rx(cb, params->chip_id, params->port, 1);
14250 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
14262 static elink_status_t elink_8073_common_init_phy(struct elink_dev *cb,
14273 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP);
14274 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE);
14276 elink_ext_phy_hw_reset(cb, port);
14292 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base,
14295 ELINK_DEBUG_P0(cb, "populate_phy failed\n");
14299 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 +
14309 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2,
14314 elink_cl45_write(cb, &phy[port],
14321 MSLEEP(cb, 150);
14338 ELINK_DEBUG_P1(cb, "Loading spirom for phy address 0x%x\n",
14340 if (elink_8073_8727_external_rom_boot(cb, phy_blk[port],
14345 elink_cl45_read(cb, phy_blk[port],
14350 elink_cl45_write(cb, phy_blk[port],
14359 MSLEEP(cb, 600);
14365 elink_cl45_read(cb, phy_blk[port],
14369 elink_cl45_write(cb, phy_blk[port],
14372 MSLEEP(cb, 15);
14375 elink_cl45_read(cb, phy_blk[port],
14378 elink_cl45_write(cb, phy_blk[port],
14383 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2,
14390 static elink_status_t elink_8726_common_init_phy(struct elink_dev *cb,
14400 val = REG_RD(cb, MISC_REG_GPIO_EVENT_EN);
14403 REG_WR(cb, MISC_REG_GPIO_EVENT_EN, val);
14405 elink_ext_phy_hw_reset(cb, 0);
14406 MSLEEP(cb, 5);
14419 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base,
14422 ELINK_DEBUG_P0(cb, "populate phy failed\n");
14427 elink_cl45_write(cb, &phy,
14432 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_0,
14441 static void elink_get_ext_phy_reset_gpio(struct elink_dev *cb, u32 shmem_base,
14445 u32 phy_gpio_reset = REG_RD(cb, shmem_base +
14487 static elink_status_t elink_8727_common_init_phy(struct elink_dev *cb,
14497 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP);
14498 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE);
14506 elink_get_ext_phy_reset_gpio(cb, shmem_base_path[0],
14513 ELINK_SET_GPIO(cb, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
14515 MSLEEP(cb, 1);
14516 ELINK_SET_GPIO(cb, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
14519 MSLEEP(cb, 5);
14537 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base,
14540 ELINK_DEBUG_P0(cb, "populate phy failed\n");
14544 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 +
14553 elink_cl45_write(cb, &phy[port],
14558 MSLEEP(cb, 150);
14572 ELINK_DEBUG_P1(cb, "Loading spirom for phy address 0x%x\n",
14574 if (elink_8073_8727_external_rom_boot(cb, phy_blk[port],
14578 elink_cl45_write(cb, phy_blk[port],
14588 static elink_status_t elink_84833_common_init_phy(struct elink_dev *cb,
14595 reset_gpios = elink_84833_get_reset_gpios(cb, shmem_base_path, chip_id);
14597 ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
14598 USLEEP(cb, 10);
14599 ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
14600 ELINK_DEBUG_P1(cb, "84833 reset pulse on pin values 0x%x\n",
14606 static elink_status_t elink_84833_pre_init_phy(struct elink_dev *cb,
14613 elink_cl45_read(cb, phy,
14618 MSLEEP(cb, 1);
14621 ELINK_DEBUG_P0(cb, "84833 reset timeout\n");
14626 elink_cl45_read(cb, phy,
14630 elink_cl45_write(cb, phy,
14635 elink_save_848xx_spirom_version(phy, cb, port);
14639 elink_status_t elink_pre_init_phy(struct elink_dev *cb,
14647 if (elink_populate_phy(cb, ELINK_EXT_PHY1, shmem_base, shmem2_base,
14649 ELINK_DEBUG_P0(cb, "populate_phy failed\n");
14652 elink_set_mdio_clk(cb, chip_id, phy.mdio_ctrl);
14656 rc = elink_84833_pre_init_phy(cb, &phy, port);
14665 static elink_status_t elink_ext_phy_common_init(struct elink_dev *cb, u32 shmem_base_path[],
14674 rc = elink_8073_common_init_phy(cb, shmem_base_path,
14681 rc = elink_8727_common_init_phy(cb, shmem_base_path,
14692 rc = elink_8726_common_init_phy(cb, shmem_base_path,
14703 rc = elink_84833_common_init_phy(cb, shmem_base_path,
14712 ELINK_DEBUG_P1(cb,
14719 elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
14726 static elink_status_t elink_warpcore_common_init(struct elink_dev *cb,
14738 REG_WR(cb, MISC_REG_LCPLL_E40_PWRDWN, 0);
14740 MSLEEP(cb, 1);
14741 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_ANA, 1);
14742 MSLEEP(cb, 1);
14743 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_DIG, 1);
14745 ELINK_DEBUG_P0(cb, "Resetting Warpcore\n");
14747 if (elink_reset_warpcore(cb) != ELINK_STATUS_OK)
14751 if (elink_populate_phy(cb, phy_index, shmem_base_path[0],
14754 ELINK_DEBUG_P0(cb, "populate phy failed\n");
14759 REG_WR(cb, MISC_REG_WC0_CTRL_MD_ST, 0);
14761 wc_lane_config = REG_RD(cb, shmem_base_path[0] +
14767 elink_warpcore_powerdown_secondport_lanes(cb, &phy);
14770 elink_warpcore_sequencer(cb, &phy, 0);
14772 elink_warpcore_set_lane_swap(cb, &phy, wc_lane_config);
14773 elink_warpcore_set_lane_polarity(cb, &phy, wc_lane_config);
14776 elink_warpcore_set_dual_mode(cb, &phy, shmem_base_path[0]);
14778 elink_warpcore_set_quad_mode(cb, &phy);
14781 rc = elink_warpcore_load_uc(cb, &phy);
14792 CL22_WR_OVER_CL45(cb, &phy, MDIO_REG_BANK_AER_BLOCK,
14794 elink_cl45_read(cb, &phy, MDIO_WC_DEVAD,
14807 elink_cl45_write(cb, &phy, MDIO_WC_DEVAD,
14812 elink_cl45_write(cb, &phy, MDIO_WC_DEVAD,
14816 elink_warpcore_sequencer(cb, &phy, 1);
14823 elink_status_t elink_common_init_phy(struct elink_dev *cb, u32 shmem_base_path[],
14838 elink_set_mdio_clk(cb, chip_id, GRCBASE_EMAC0);
14839 elink_set_mdio_clk(cb, chip_id, GRCBASE_EMAC1);
14840 ELINK_DEBUG_P0(cb, "Begin common phy init\n");
14843 val = REG_RD(cb, MISC_REG_GEN_PURP_HWG);
14844 REG_WR(cb, MISC_REG_GEN_PURP_HWG, val | 1);
14848 phy_ver = REG_RD(cb, shmem_base_path[0] +
14852 ELINK_DEBUG_P1(cb, "Not doing common init; phy ver is 0x%x\n",
14859 rc |= elink_warpcore_common_init(cb, shmem_base_path,
14867 ext_phy_config = elink_get_ext_phy_config(cb,
14871 rc |= elink_ext_phy_common_init(cb, shmem_base_path,
14886 struct elink_dev *cb = params->cb;
14891 cfg_pin = (REG_RD(cb, params->shmem_base +
14898 if (elink_get_cfg_pin(cb, cfg_pin, &pin_val) != ELINK_STATUS_OK)
14904 elink_cb_event_log(cb, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
14925 struct elink_dev *cb = params->cb;
14936 ELINK_DEBUG_P0(cb, "Analyze Remote Fault\n");
14939 ELINK_DEBUG_P0(cb, "Analyze TX Fault\n");
14942 ELINK_DEBUG_P0(cb, "Analyze UNKNOWN\n");
14944 ELINK_DEBUG_P3(cb, "Link changed:[%x %x]->%x\n", vars->link_up,
14961 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
14974 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
14991 elink_cb_notify_link_changed(cb);
15013 struct elink_dev *cb = params->cb;
15018 (REG_RD(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
15022 (REG_RD(cb, MISC_REG_RESET_REG_2) &
15032 REG_WR(cb, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
15033 REG_WR(cb, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
15036 if (REG_RD(cb, mac_base + XMAC_REG_RX_LSS_STATUS))
15042 } else if (REG_RD(cb, MISC_REG_RESET_REG_2) &
15055 REG_RD_DMAE(cb, mac_base + lss_status_reg, wb_data, 2);
15069 struct elink_dev *cb = params->cb;
15074 cfg_pin = (REG_RD(cb, params->shmem_base + OFFSETOF(struct shmem_region,
15079 if (elink_get_cfg_pin(cb, cfg_pin, &value)) {
15080 ELINK_DEBUG_P1(cb, "Failed to read pin 0x%02x\n", cfg_pin);
15102 ELINK_DEBUG_P1(cb, "Change TX_Fault LED: ->%x\n",
15115 struct elink_dev *cb = params->cb;
15116 ELINK_DEBUG_P0(cb, "KR2 recovery\n");
15126 struct elink_dev *cb = params->cb;
15144 ELINK_DEBUG_P0(cb, "No sigdet\n");
15150 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
15152 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
15154 elink_cl45_read(cb, phy, MDIO_AN_DEVAD,
15162 ELINK_DEBUG_P0(cb, "No BP\n");
15178 ELINK_DEBUG_P2(cb, "BP=0x%x, NP=0x%x\n", base_page,
15187 ELINK_DEBUG_P2(cb, "BP=0x%x, NP=0x%x\n", base_page, next_page);
15200 struct elink_dev *cb = params->cb;
15207 ELINK_DEBUG_P0(cb, "Fault detection failed\n");
15239 if ((REG_RD(cb, params->shmem_base +
15261 u8 elink_fan_failure_det_req(struct elink_dev *cb,
15270 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base,
15273 ELINK_DEBUG_P0(cb, "populate phy failed\n");
15286 elink_set_mdio_emac_per_phy(params->cb, params);
15294 elink_cl45_write(params->cb, ¶ms->phy[phy_index],
15307 struct elink_dev *cb = params->cb;
15309 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
15327 void elink_init_mod_abs_int(struct elink_dev *cb, struct elink_vars *vars,
15335 if (elink_get_mod_abs_int_cfg(cb, chip_id,
15345 if (elink_populate_phy(cb, phy_index, shmem_base,
15348 ELINK_DEBUG_P0(cb, "populate phy failed\n");
15363 ELINK_SET_GPIO(cb, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
15365 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP);
15366 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE);
15375 REG_WR(cb, sync_offset, vars->aeu_int_mask);
15377 ELINK_DEBUG_P3(cb, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
15386 aeu_mask = REG_RD(cb, offset);
15388 REG_WR(cb, offset, aeu_mask);
15391 val = REG_RD(cb, MISC_REG_GPIO_EVENT_EN);
15393 REG_WR(cb, MISC_REG_GPIO_EVENT_EN, val);
15515 void set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val)
15517 elink_set_cfg_pin(cb, pin_cfg, val);
15519 int get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val)
15521 return elink_get_cfg_pin(cb, pin_cfg, val);
15526 struct elink_dev *cb = params->cb;
15531 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK,
15534 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD,
15540 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD,