Lines Matching defs:bgep
113 bge_phydump(bge_t *bgep, uint16_t mii_status, uint16_t aux)
118 ASSERT(mutex_owned(bgep->genlock));
123 regs[i] = bge_mii_get16(bgep, i);
153 bge_phy_toggle_auxctl_smdsp(bge_t *bgep,
158 val = bge_mii_get16(bgep, MII_AUX_CONTROL);
166 bge_mii_put16(bgep, MII_AUX_CONTROL, (val | MII_AUX_CTRL_TX_6DB));
175 bge_phy_probe(bge_t *bgep)
181 BGE_TRACE(("bge_phy_probe($%p)", (void *)bgep));
183 ASSERT(mutex_owned(bgep->genlock));
185 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR);
187 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR);
203 miicfg = bge_mii_get16(bgep, MII_STATUS);
232 bge_phy_reset(bge_t *bgep)
237 BGE_TRACE(("bge_phy_reset($%p)", (void *)bgep));
239 ASSERT(mutex_owned(bgep->genlock));
241 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
244 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ);
245 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */
252 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET);
255 control = bge_mii_get16(bgep, MII_CONTROL);
260 if (DEVICE_5906_SERIES_CHIPSETS(bgep))
261 (void) bge_adj_volt_5906(bgep);
273 bge_phy_powerdown(bge_t *bgep)
277 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_PWRDN);
296 bge_phy_macro_wait(bge_t *bgep)
301 if ((bge_mii_get16(bgep, 0x16) & 0x1000) == 0)
350 bge_phy_locked_up(bge_t *bgep)
363 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200);
365 bge_mii_put16(bgep, 0x16, 0x0002);
372 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].lo);
373 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].hi);
380 bge_mii_put16(bgep, 0x16, 0x0202);
381 bge_phy_macro_wait(bgep);
388 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200);
394 bge_mii_put16(bgep, 0x16, 0x0082);
395 bge_phy_macro_wait(bgep);
398 bge_mii_put16(bgep, 0x16, 0x0802);
399 bge_phy_macro_wait(bgep);
411 dataLo = bge_mii_get16(bgep, 0x15) & 0x7fff;
412 dataHi = bge_mii_get16(bgep, 0x15) & 0x003f;
413 bge_phy_macro_wait(bgep);
441 bge_phy_reset_and_check(bge_t *bgep)
452 reset_success = bge_phy_reset(bgep);
466 extctrl = bge_mii_get16(bgep, 0x10);
467 bge_mii_put16(bgep, 0x10, extctrl | 0x3000);
470 bge_mii_put16(bgep, 0x0, 0x0140);
473 gigctrl = bge_mii_get16(bgep, 0x9);
474 bge_mii_put16(bgep, 0x9, 0x1800);
477 bge_mii_put16(bgep, 0x18, 0x0c00); /* "the ADC fix" */
480 bge_mii_put16(bgep, 0x17, 0x201f);
481 bge_mii_put16(bgep, 0x15, 0x2aaa);
484 bge_mii_put16(bgep, 0x17, 0x000a);
485 bge_mii_put16(bgep, 0x15, 0x0323); /* "the Gamma fix" */
488 bge_mii_put16(bgep, 0x17, 0x8005);
489 bge_mii_put16(bgep, 0x15, 0x0800);
492 phy_locked = bge_phy_locked_up(bgep);
500 BGE_REPORT((bgep, "PHY didn't reset!"));
502 BGE_REPORT((bgep, "PHY locked up!"));
506 bge_mii_put16(bgep, 0x17, 0x8005);
507 bge_mii_put16(bgep, 0x15, 0x0000);
510 bge_mii_put16(bgep, 0x17, 0x8200);
511 bge_mii_put16(bgep, 0x16, 0x0000);
514 bge_mii_put16(bgep, 0x18, 0x0400);
517 bge_mii_put16(bgep, 0x9, gigctrl);
520 extctrl = bge_mii_get16(bgep, 0x10);
521 bge_mii_put16(bgep, 0x10, extctrl & ~0x3000);
523 if (DEVICE_5906_SERIES_CHIPSETS(bgep))
524 (void) bge_adj_volt_5906(bgep);
527 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
529 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE);
534 bge_phy_tweak_gmii(bge_t *bgep)
537 bge_mii_put16(bgep, 0x1c, 0x8d68);
538 bge_mii_put16(bgep, 0x1c, 0x8d68);
543 bge_phy_bit_err_fix(bge_t *bgep)
545 bge_mii_put16(bgep, 0x18, 0x0c00);
546 bge_mii_put16(bgep, 0x17, 0x000a);
547 bge_mii_put16(bgep, 0x15, 0x310b);
548 bge_mii_put16(bgep, 0x17, 0x201f);
549 bge_mii_put16(bgep, 0x15, 0x9506);
550 bge_mii_put16(bgep, 0x17, 0x401f);
551 bge_mii_put16(bgep, 0x15, 0x14e2);
552 bge_mii_put16(bgep, 0x18, 0x0400);
560 bge_restart_copper(bge_t *bgep, boolean_t powerdown)
567 BGE_TRACE(("bge_restart_copper($%p, %d)", (void *)bgep, powerdown));
569 ASSERT(mutex_owned(bgep->genlock));
571 switch (MHCR_CHIP_ASIC_REV(bgep)) {
583 reset_ok = bge_phy_reset_and_check(bgep);
594 reset_ok = bge_phy_reset(bgep);
596 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
600 BGE_REPORT((bgep, "PHY failed to reset correctly"));
609 switch (bgep->chipid.asic_rev) {
614 bge_phy_tweak_gmii(bgep);
618 switch (MHCR_CHIP_ASIC_REV(bgep)) {
621 bge_phy_bit_err_fix(bgep);
625 if (!(bgep->chipid.flags & CHIP_FLAG_NO_JUMBO) &&
626 (bgep->chipid.default_mtu > BGE_DEFAULT_MTU)) {
628 extctrl = bge_mii_get16(bgep, 0x10);
629 bge_mii_put16(bgep, 0x10, extctrl | 0x1);
632 bge_mii_put16(bgep, MII_AUX_CONTROL, 0x0007);
633 auxctrl = bge_mii_get16(bgep, MII_AUX_CONTROL);
635 bge_mii_put16(bgep, MII_AUX_CONTROL, auxctrl);
655 phy_status = bge_mii_get16(bgep, MII_STATUS);
663 bge_phy_powerdown(bgep);
668 bge_eee_cap(bge_t * bgep)
670 if (!(DEVICE_5717_SERIES_CHIPSETS(bgep) ||
671 DEVICE_5725_SERIES_CHIPSETS(bgep))) {
674 bgep->chipid.device));
678 switch (CHIP_ASIC_REV_PROD_ID(bgep)) {
692 bgep->chipid.asic_rev));
698 bge_eee_init(bge_t * bgep)
702 BGE_TRACE(("bge_eee_init($%p)", (void *)bgep));
704 ASSERT(mutex_owned(bgep->genlock));
706 if (!bge_eee_cap(bgep)) {
713 if (DEVICE_5725_SERIES_CHIPSETS(bgep))
715 bge_reg_put32(bgep, EEE_LINK_IDLE_CONTROL_REG, val);
717 bge_reg_put32(bgep, EEE_CONTROL_REG, EEE_CONTROL_EXIT_20_1_US);
722 if (bgep->chipid.device != DEVICE_ID_5717)
727 if (!bgep->chipid.eee) {
731 bge_reg_put32(bgep, EEE_MODE_REG, val);
735 bge_reg_put32(bgep, EEE_DEBOUNCE_T1_CONTROL_REG,
738 bge_reg_put32(bgep, EEE_DEBOUNCE_T2_CONTROL_REG,
743 bge_eee_autoneg(bge_t * bgep, boolean_t adv_100fdx, boolean_t adv_1000fdx)
748 BGE_TRACE(("bge_eee_autoneg($%p)", (void *)bgep));
750 ASSERT(mutex_owned(bgep->genlock));
752 if (!bge_eee_cap(bgep)) {
757 val = bge_reg_get32(bgep, EEE_MODE_REG);
759 bge_reg_put32(bgep, EEE_MODE_REG, val);
761 bge_phy_toggle_auxctl_smdsp(bgep, B_TRUE);
765 if (bgep->chipid.eee) {
775 bge_mii_put16(bgep, MII_MMD_CTRL, MDIO_MMD_AN);
776 bge_mii_put16(bgep, MII_MMD_ADDRESS_DATA, MDIO_AN_EEE_ADV);
777 bge_mii_put16(bgep, MII_MMD_CTRL,
779 bge_mii_put16(bgep, MII_MMD_ADDRESS_DATA, mii_val);
782 switch (bgep->chipid.device) {
792 bge_phydsp_write(bgep, MII_DSP_TAP26, mii_val);
797 mii_val = bge_phydsp_read(bgep, MII_DSP_CH34TP2);
798 bge_phydsp_write(bgep, MII_DSP_CH34TP2,
802 bge_phy_toggle_auxctl_smdsp(bgep, B_FALSE);
806 bge_eee_adjust(bge_t * bgep)
811 BGE_TRACE(("bge_eee_adjust($%p, %d)", (void *)bgep));
813 ASSERT(mutex_owned(bgep->genlock));
815 if (!bge_eee_cap(bgep)) {
819 bgep->eee_lpi_wait = 0;
822 if (bgep->param_link_up) {
830 if (bgep->param_link_speed == 1000) {
832 bge_reg_put32(bgep, EEE_CONTROL_REG,
834 } else if (bgep->param_link_speed == 100) {
836 bge_reg_put32(bgep, EEE_CONTROL_REG,
841 bge_mii_put16(bgep, MII_MMD_CTRL, MDIO_MMD_AN);
842 bge_mii_put16(bgep, MII_MMD_ADDRESS_DATA,
844 bge_mii_put16(bgep, MII_MMD_CTRL,
846 mii_val = bge_mii_get16(bgep, MII_MMD_ADDRESS_DATA);
852 bgep->eee_lpi_wait = 2;
860 if (!bgep->eee_lpi_wait) {
861 if (bgep->param_link_up) {
862 bge_phy_toggle_auxctl_smdsp(bgep, B_TRUE);
863 bge_phydsp_write(bgep, MII_DSP_TAP26, 0);
864 bge_phy_toggle_auxctl_smdsp(bgep, B_FALSE);
868 val = bge_reg_get32(bgep, EEE_MODE_REG);
870 bge_reg_put32(bgep, EEE_MODE_REG, val);
875 bge_eee_enable(bge_t * bgep)
881 if (bgep->param_link_speed == 1000) {
882 bge_phy_toggle_auxctl_smdsp(bgep, B_TRUE);
883 bge_phydsp_write(bgep, MII_DSP_TAP26,
885 bge_phy_toggle_auxctl_smdsp(bgep, B_FALSE);
888 val = bge_reg_get32(bgep, EEE_MODE_REG);
890 bge_reg_put32(bgep, EEE_MODE_REG, val);
907 bge_update_copper(bge_t *bgep)
924 BGE_TRACE(("bge_update_copper($%p)", (void *)bgep));
926 ASSERT(mutex_owned(bgep->genlock));
933 bgep->param_adv_autoneg,
934 bgep->param_adv_pause, bgep->param_adv_asym_pause,
935 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx,
936 bgep->param_adv_100fdx, bgep->param_adv_100hdx,
937 bgep->param_adv_10fdx, bgep->param_adv_10hdx));
950 switch (bgep->param_loop_mode) {
953 adv_autoneg = bgep->param_adv_autoneg;
954 adv_pause = bgep->param_adv_pause;
955 adv_asym_pause = bgep->param_adv_asym_pause;
956 adv_1000fdx = bgep->param_adv_1000fdx;
957 adv_1000hdx = bgep->param_adv_1000hdx;
958 adv_100fdx = bgep->param_adv_100fdx;
959 adv_100hdx = bgep->param_adv_100hdx;
960 adv_10fdx = bgep->param_adv_10fdx;
961 adv_10hdx = bgep->param_adv_10hdx;
972 bgep->param_link_duplex = LINK_DUPLEX_FULL;
974 switch (bgep->param_loop_mode) {
976 bgep->param_link_speed = 1000;
984 bgep->param_link_speed = 100;
990 bgep->param_link_speed = 10;
996 bgep->param_link_speed = 1000;
1002 bgep->param_link_speed = 1000;
1084 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) == DDI_FAILURE)
1086 bge_mii_put16(bgep, MII_AN_ADVERT, anar);
1088 bge_mii_put16(bgep, MII_AUX_CONTROL, auxctrl);
1089 bge_mii_put16(bgep, MII_MSCONTROL, gigctrl);
1090 bge_mii_put16(bgep, MII_CONTROL, control);
1102 switch (bgep->chipid.device) {
1116 if (bgep->param_loop_mode == BGE_LOOP_NONE)
1117 bge_mii_put16(bgep, MII_AUX_CONTROL,
1126 bge_eee_autoneg(bgep, adv_100fdx, adv_1000fdx);
1132 bge_check_copper(bge_t *bgep, boolean_t recheck)
1148 mii_status = bge_mii_get16(bgep, MII_STATUS);
1150 emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG);
1151 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, emac_status);
1155 bgep->link_state, UPORDOWN(bgep->param_link_up), mii_status,
1156 bgep->phy_gen_status, emac_status));
1163 if (mii_status == bgep->phy_gen_status && !recheck) {
1174 aux = bge_mii_get16(bgep, MII_AUX_STATUS);
1176 BGE_CDB(bge_phydump, (bgep, mii_status, aux));
1184 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
1204 bgep->phy_aux_status = aux;
1205 bgep->phy_gen_status = mii_status;
1210 mii_status = bge_mii_get16(bgep, MII_STATUS);
1212 } while (mii_status != bgep->phy_gen_status);
1217 bgep->param_lp_autoneg = B_FALSE;
1218 bgep->param_lp_1000fdx = B_FALSE;
1219 bgep->param_lp_1000hdx = B_FALSE;
1220 bgep->param_lp_100fdx = B_FALSE;
1221 bgep->param_lp_100hdx = B_FALSE;
1222 bgep->param_lp_10fdx = B_FALSE;
1223 bgep->param_lp_10hdx = B_FALSE;
1224 bgep->param_lp_pause = B_FALSE;
1225 bgep->param_lp_asym_pause = B_FALSE;
1226 bgep->param_link_autoneg = B_FALSE;
1227 bgep->param_link_tx_pause = B_FALSE;
1228 if (bgep->param_adv_autoneg)
1229 bgep->param_link_rx_pause = B_FALSE;
1231 bgep->param_link_rx_pause = bgep->param_adv_pause;
1238 bgep->param_lp_autoneg = B_TRUE;
1239 bgep->param_link_autoneg = B_TRUE;
1240 bgep->param_link_tx_pause = BIS(aux, MII_AUX_STATUS_TX_PAUSE);
1241 bgep->param_link_rx_pause = BIS(aux, MII_AUX_STATUS_RX_PAUSE);
1243 aux = bge_mii_get16(bgep, MII_MSSTATUS);
1244 bgep->param_lp_1000fdx = BIS(aux, MII_MSSTATUS_LP1000T_FD);
1245 bgep->param_lp_1000hdx = BIS(aux, MII_MSSTATUS_LP1000T);
1247 aux = bge_mii_get16(bgep, MII_AN_LPABLE);
1248 bgep->param_lp_100fdx = BIS(aux, MII_ABILITY_100BASE_TX_FD);
1249 bgep->param_lp_100hdx = BIS(aux, MII_ABILITY_100BASE_TX);
1250 bgep->param_lp_10fdx = BIS(aux, MII_ABILITY_10BASE_T_FD);
1251 bgep->param_lp_10hdx = BIS(aux, MII_ABILITY_10BASE_T);
1252 bgep->param_lp_pause = BIS(aux, MII_ABILITY_PAUSE);
1253 bgep->param_lp_asym_pause = BIS(aux, MII_ABILITY_ASMPAUSE);
1264 UPORDOWN(bgep->param_link_up),
1265 bgep->param_link_speed,
1266 bgep->param_link_duplex));
1270 bgep->param_link_up = linkup;
1271 bgep->link_state = LINK_STATE_UNKNOWN;
1272 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
1273 if (bgep->phy_aux_status & MII_AUX_STATUS_NEG_ENABLED_5906) {
1274 bgep->param_link_speed =
1276 bgep->param_link_duplex =
1279 bgep->param_link_speed = (bgep->phy_aux_status &
1281 bgep->param_link_duplex = (bgep->phy_aux_status &
1286 bgep->param_link_speed = bge_copper_link_speed[mode];
1287 bgep->param_link_duplex = bge_copper_link_duplex[mode];
1290 bge_eee_adjust(bgep);
1292 bge_log(bgep, "bge_check_copper: link now %s speed %d duplex %d",
1293 UPORDOWN(bgep->param_link_up),
1294 bgep->param_link_speed,
1295 bgep->param_link_duplex);
1319 bge_restart_serdes(bge_t *bgep, boolean_t powerdown)
1323 BGE_TRACE(("bge_restart_serdes($%p, %d)", (void *)bgep, powerdown));
1325 ASSERT(mutex_owned(bgep->genlock));
1331 macmode = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
1334 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1335 DEVICE_5725_SERIES_CHIPSETS(bgep) ||
1336 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1341 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
1348 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TBI_LOOPBACK);
1349 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_COMMA_DETECT);
1350 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE);
1361 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE);
1362 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 0);
1363 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS);
1365 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS);
1366 bgep->serdes_lpadv = AUTONEG_CODE_FAULT_ANEG_ERR;
1367 bgep->serdes_status = ~0U;
1387 bge_update_serdes(bge_t *bgep)
1398 BGE_TRACE(("bge_update_serdes($%p)", (void *)bgep));
1400 ASSERT(mutex_owned(bgep->genlock));
1407 bgep->param_adv_autoneg,
1408 bgep->param_adv_pause, bgep->param_adv_asym_pause,
1409 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx,
1410 bgep->param_adv_100fdx, bgep->param_adv_100hdx,
1411 bgep->param_adv_10fdx, bgep->param_adv_10hdx));
1428 switch (bgep->param_loop_mode) {
1431 adv_autoneg = bgep->param_adv_autoneg;
1432 adv_pause = bgep->param_adv_pause;
1433 adv_asym_pause = bgep->param_adv_asym_pause;
1434 adv_1000fdx = bgep->param_adv_1000fdx;
1435 adv_1000hdx = bgep->param_adv_1000hdx;
1477 bgep->param_adv_1000fdx = adv_1000fdx;
1478 bgep->param_link_duplex = LINK_DUPLEX_FULL;
1479 bgep->param_link_speed = 1000;
1483 bgep->param_adv_1000hdx = adv_1000hdx;
1484 bgep->param_link_duplex = LINK_DUPLEX_HALF;
1485 bgep->param_link_speed = 1000;
1498 bgep->serdes_advert = advert;
1499 (void) bge_restart_serdes(bgep, B_FALSE);
1500 bge_reg_set32(bgep, SERDES_CONTROL_REG, serdes);
1515 bge_autoneg_serdes(bge_t *bgep)
1519 bgep->serdes_lpadv = bge_reg_get32(bgep, RX_1000BASEX_AUTONEG_REG);
1520 ack = BIS(bgep->serdes_lpadv, AUTONEG_CODE_ACKNOWLEDGE);
1529 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG,
1530 bgep->serdes_advert | AUTONEG_CODE_ACKNOWLEDGE);
1531 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
1539 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG,
1544 bgep->serdes_lpadv,
1546 bgep->serdes_advert));
1550 bge_check_serdes(bge_t *bgep, boolean_t recheck)
1556 boolean_t linkup_old = bgep->param_link_up;
1566 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1567 DEVICE_5725_SERIES_CHIPSETS(bgep) ||
1568 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1569 tx_status = bge_reg_get32(bgep,
1572 emac_status = bge_reg_get32(bgep,
1574 bgep->serdes_status = emac_status;
1577 (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1578 DEVICE_5725_SERIES_CHIPSETS(bgep))) {
1582 bge_reg_put32(bgep,
1605 emac_status = bge_reg_get32(bgep,
1607 bge_reg_put32(bgep,
1612 bgep->link_state, UPORDOWN(bgep->param_link_up),
1613 emac_status, bgep->serdes_status));
1619 bgep->serdes_status = emac_status;
1637 if (bgep->param_link_up && linkup)
1642 bgep->serdes_status, emac_status,
1650 bge_autoneg_serdes(bgep);
1682 bgep->param_lp_autoneg = B_FALSE;
1683 bgep->param_lp_1000fdx = B_FALSE;
1684 bgep->param_lp_1000hdx = B_FALSE;
1685 bgep->param_lp_100fdx = B_FALSE;
1686 bgep->param_lp_100hdx = B_FALSE;
1687 bgep->param_lp_10fdx = B_FALSE;
1688 bgep->param_lp_10hdx = B_FALSE;
1689 bgep->param_lp_pause = B_FALSE;
1690 bgep->param_lp_asym_pause = B_FALSE;
1691 bgep->param_link_autoneg = B_FALSE;
1692 bgep->param_link_tx_pause = B_FALSE;
1693 if (bgep->param_adv_autoneg)
1694 bgep->param_link_rx_pause = B_FALSE;
1696 bgep->param_link_rx_pause = bgep->param_adv_pause;
1701 lpadv = bgep->serdes_lpadv;
1706 bgep->param_lp_autoneg = B_TRUE;
1707 bgep->param_lp_1000fdx = BIS(lpadv, AUTONEG_CODE_FULL_DUPLEX);
1708 bgep->param_lp_1000hdx = BIS(lpadv, AUTONEG_CODE_HALF_DUPLEX);
1709 bgep->param_lp_pause = BIS(lpadv, AUTONEG_CODE_PAUSE);
1710 bgep->param_lp_asym_pause = BIS(lpadv, AUTONEG_CODE_ASYM_PAUSE);
1715 bgep->param_link_autoneg = B_TRUE;
1716 if (bgep->param_adv_pause &&
1717 bgep->param_lp_pause) {
1718 bgep->param_link_tx_pause = B_TRUE;
1719 bgep->param_link_rx_pause = B_TRUE;
1721 if (bgep->param_adv_asym_pause &&
1722 bgep->param_lp_asym_pause) {
1723 if (bgep->param_adv_pause)
1724 bgep->param_link_rx_pause = B_TRUE;
1725 if (bgep->param_lp_pause)
1726 bgep->param_link_tx_pause = B_TRUE;
1738 UPORDOWN(bgep->param_link_up),
1739 bgep->param_link_speed,
1740 bgep->param_link_duplex));
1743 bgep->param_link_up = B_TRUE;
1744 bgep->param_link_speed = 1000;
1745 if (bgep->param_adv_1000fdx)
1746 bgep->param_link_duplex = LINK_DUPLEX_FULL;
1748 bgep->param_link_duplex = LINK_DUPLEX_HALF;
1749 if (bgep->param_lp_autoneg && !bgep->param_lp_1000fdx)
1750 bgep->param_link_duplex = LINK_DUPLEX_HALF;
1752 bgep->param_link_up = B_FALSE;
1753 bgep->param_link_speed = 0;
1754 bgep->param_link_duplex = LINK_DUPLEX_UNKNOWN;
1756 bgep->link_state = LINK_STATE_UNKNOWN;
1758 bge_log(bgep, "bge_check_serdes: link now %s speed %d duplex %d",
1759 UPORDOWN(bgep->param_link_up),
1760 bgep->param_link_speed,
1761 bgep->param_link_duplex);
1784 bge_phys_init(bge_t *bgep)
1788 BGE_TRACE(("bge_phys_init($%p)", (void *)bgep));
1790 mutex_enter(bgep->genlock);
1798 bgep->phy_mii_addr = 1;
1800 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1801 bgep->phy_mii_addr = (bgep->pci_func + 1);
1802 regval = bge_reg_get32(bgep, SGMII_STATUS_REG);
1804 bgep->phy_mii_addr += 7; /* sgmii */
1807 if (bge_phy_probe(bgep)) {
1808 bgep->chipid.flags &= ~CHIP_FLAG_SERDES;
1809 bgep->physops = &copper_ops;
1811 bgep->chipid.flags |= CHIP_FLAG_SERDES;
1812 bgep->physops = &serdes_ops;
1815 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) != DDI_SUCCESS) {
1816 mutex_exit(bgep->genlock);
1819 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) {
1820 mutex_exit(bgep->genlock);
1823 mutex_exit(bgep->genlock);
1831 bge_phys_reset(bge_t *bgep)
1833 BGE_TRACE(("bge_phys_reset($%p)", (void *)bgep));
1835 mutex_enter(bgep->genlock);
1836 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) != DDI_SUCCESS)
1837 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
1838 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
1839 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
1840 mutex_exit(bgep->genlock);
1850 bge_phys_idle(bge_t *bgep)
1852 BGE_TRACE(("bge_phys_idle($%p)", (void *)bgep));
1854 ASSERT(mutex_owned(bgep->genlock));
1855 return ((*bgep->physops->phys_restart)(bgep, B_TRUE));
1871 bge_phys_update(bge_t *bgep)
1873 BGE_TRACE(("bge_phys_update($%p)", (void *)bgep));
1875 ASSERT(mutex_owned(bgep->genlock));
1876 return ((*bgep->physops->phys_update)(bgep));
1896 bge_phys_check(bge_t *bgep)
1898 BGE_TRACE(("bge_phys_check($%p)", (void *)bgep));
1900 ASSERT(mutex_owned(bgep->genlock));
1907 return ((*bgep->physops->phys_check)(bgep,
1908 (bgep->link_state == LINK_STATE_UNKNOWN)));