Lines Matching refs:control
219 * Reinitialise control variables ...
279 * Reinitialise control variables ...
324 * Finally, reinitialise the ring control variables ...
1580 if ((rulep[i].control & RECV_RULE_CTL_ENABLE) == 0 &&
1581 (rulep[i+1].control & RECV_RULE_CTL_ENABLE) == 0)
1588 rulep[i].control = RULE_DEST_MAC_1(ring) | RECV_RULE_CTL_AND;
1590 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep[i].control);
1594 rulep[i+1].control = RULE_DEST_MAC_2(ring);
1596 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i+1), rulep[i+1].control);
1651 rulep[start].control = 0;
1653 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(start), rulep[start].control);
1656 rulep[start].control = 0;
1658 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(start), rulep[start].control);