Lines Matching defs:read
171 * Config space read-modify-write routines
1230 * and then re-read the register to get the final value of the
1244 * value read after the 5us delay. This seems to be due to the
1249 * the data from the original read that showed START clear.
1436 * All OK; read the SEEPROM data register, then write back
1437 * the value read from the address register in order to
1538 * All OK; read the data from the Flash read register
1856 bge_nvmem_access_cmd(bge_t *bgep, boolean_t read)
1866 return (read ? BGE_SEE_READ : BGE_SEE_WRITE);
1870 return (read ? BGE_FLASH_READ : BGE_FLASH_WRITE);
3120 * it will then read back as 1 while the reset is in progress, but
3124 * will continue to read back as 0 until the state machine is running.
3127 * it will continue to read back as 1 until the state machine actually
3164 * be written with 1; it will then read back as 1 while the reset is
3167 * This code sets the bit, then polls for it to read back as zero.
3247 * by following it with a read (even to config space)
3828 * While we're at it, we also read the MAC address register;
4183 * those read into the local structure <chipid>, 'cos
4339 * Step 24: set DMA read/write control register