Lines Matching defs:bgep
35 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset)))
36 #define APE_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->ape_regs+(offset)))
176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits);
180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits)
185 (void *)bgep, regno, bits));
187 regval = pci_config_get16(bgep->cfg_handle, regno);
190 (void *)bgep, regno, bits, regval, regval & ~bits));
193 pci_config_put16(bgep->cfg_handle, regno, regval);
198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
207 (void *)bgep, regno, bits));
209 regval = pci_config_get32(bgep->cfg_handle, regno);
212 (void *)bgep, regno, bits, regval, regval & ~bits));
215 pci_config_put32(bgep->cfg_handle, regno, regval);
234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
238 bge_ind_get32(bge_t *bgep, bge_regno_t regno)
242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
245 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
246 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
250 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
251 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
254 (void *)bgep, regno, val));
261 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
265 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val)
268 (void *)bgep, regno, val));
272 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
273 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
277 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
278 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
285 static void bge_pci_check(bge_t *bgep);
289 bge_pci_check(bge_t *bgep)
293 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT);
296 (void *)bgep, pcistatus));
324 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
328 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
339 (void *)bgep, (void *)cidp, enable_dma));
360 handle = bgep->cfg_handle;
368 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
369 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
378 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
379 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
396 if (pci_config_get16(bgep->cfg_handle, PCI_CONF_DEVID) ==
477 if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
486 bgep->asf_wordswapped = B_FALSE;
491 if (bgep->ape_enabled) {
495 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PCISTATE, pci_state);
509 command = bgep->chipid.command | PCI_COMM_MAE;
529 if (bgep->chipid.pci_type == BGE_PCI_E) {
560 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED);
563 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
564 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723,
566 } else if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
567 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
568 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717,
571 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL,
601 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
605 bge_reg_get32(bge_t *bgep, bge_regno_t regno)
608 (void *)bgep, regno));
610 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)));
613 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
617 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
620 (void *)bgep, regno, data));
622 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data);
623 BGE_PCICHK(bgep);
626 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
630 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
635 (void *)bgep, regno, bits));
637 regval = bge_reg_get32(bgep, regno);
639 bge_reg_put32(bgep, regno, regval);
642 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
646 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
651 (void *)bgep, regno, bits));
653 regval = bge_reg_get32(bgep, regno);
655 bge_reg_put32(bgep, regno, regval);
658 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno);
662 bge_reg_get64(bge_t *bgep, bge_regno_t regno)
667 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
669 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
670 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
671 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
673 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
675 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
678 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
679 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
680 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
681 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
683 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
685 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
688 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
696 (void *)bgep, regno, regval));
701 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data);
705 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
708 (void *)bgep, regno, data));
715 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
717 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
718 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
719 ddi_put32(bgep->io_handle,
720 PIO_ADDR(bgep, regno), (uint32_t)data);
721 BGE_PCICHK(bgep);
722 ddi_put32(bgep->io_handle,
723 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32));
726 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
729 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
730 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
731 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
732 ddi_put32(bgep->io_handle,
733 PIO_ADDR(bgep, regno + 4), (uint32_t)data);
734 BGE_PCICHK(bgep);
735 ddi_put32(bgep->io_handle,
736 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32));
738 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
741 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
744 BGE_PCICHK(bgep);
751 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
755 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
760 (void *)bgep, addr, rcbp->host_ring_addr,
766 bge_reg_put64(bgep, addr, *p++);
767 bge_reg_put64(bgep, addr+8, *p);
770 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data);
774 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data)
776 if (DEVICE_5906_SERIES_CHIPSETS(bgep))
780 (void *)bgep, regno, data));
790 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data);
792 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data);
794 BGE_PCICHK(bgep);
797 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno);
801 bge_mbx_get(bge_t *bgep, bge_regno_t regno)
805 if (DEVICE_5906_SERIES_CHIPSETS(bgep))
809 (void *)bgep, regno));
812 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4));
814 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
816 BGE_PCICHK(bgep);
819 (void *)bgep, regno, val32));
827 void bge_led_mark(bge_t *bgep);
831 bge_led_mark(bge_t *bgep)
843 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
845 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
847 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
862 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base);
866 bge_nic_setwin(bge_t *bgep, bge_regno_t base)
871 (void *)bgep, base));
879 cidp = &bgep->chipid;
882 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0))
885 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ?
889 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
890 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
894 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base);
897 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr);
901 bge_nic_get32(bge_t *bgep, bge_regno_t addr)
906 if (bgep->asf_enabled && !bgep->asf_wordswapped) {
916 data = bge_nic_read32(bgep, addr);
918 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
922 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
926 (void *)bgep, addr, data));
931 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
935 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data)
938 (void *)bgep, addr, data));
941 if (bgep->asf_enabled && !bgep->asf_wordswapped) {
951 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
952 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
955 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
957 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data);
958 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
960 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
963 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data);
964 BGE_PCICHK(bgep);
968 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr);
972 bge_nic_get64(bge_t *bgep, bge_regno_t addr)
976 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
981 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
983 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
984 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
985 data = ddi_get32(bgep->io_handle,
986 PIO_ADDR(bgep, addr + 4));
988 data |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
990 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
993 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
994 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
995 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
996 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
998 data |= ddi_get32(bgep->io_handle,
999 PIO_ADDR(bgep, addr + 4));
1001 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
1004 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
1008 (void *)bgep, addr, data));
1013 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data);
1017 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
1020 (void *)bgep, addr, data));
1022 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1027 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1029 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1030 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
1031 ddi_put32(bgep->io_handle,
1032 PIO_ADDR(bgep, addr + 4), (uint32_t)data);
1033 BGE_PCICHK(bgep);
1034 ddi_put32(bgep->io_handle,
1035 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
1037 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
1040 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1041 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1042 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
1043 ddi_put32(bgep->io_handle,
1044 PIO_ADDR(bgep, addr + 4), (uint32_t)data);
1045 BGE_PCICHK(bgep);
1046 ddi_put32(bgep->io_handle,
1047 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
1049 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
1052 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
1055 BGE_PCICHK(bgep);
1062 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
1066 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
1071 (void *)bgep, addr, rcbp->host_ring_addr,
1076 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1082 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1084 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1085 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
1086 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1088 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1090 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1092 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1096 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1097 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p);
1100 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1101 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1102 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
1103 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1105 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1107 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1109 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1112 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1113 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1116 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1117 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1120 BGE_PCICHK(bgep);
1123 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes);
1127 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes)
1130 (void *)bgep, addr, nbytes));
1135 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1139 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr),
1141 BGE_PCICHK(bgep);
1155 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno,
1160 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd)
1167 (void *)bgep, regno, data, cmd));
1169 ASSERT(mutex_owned(bgep->genlock));
1176 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT;
1188 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1191 bge_reg_put32(bgep, MI_COMMS_REG, cmd);
1197 regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1204 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1208 regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1215 regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1239 regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1252 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1267 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1271 bge_mii_get16(bge_t *bgep, bge_regno_t regno)
1274 (void *)bgep, regno));
1276 ASSERT(mutex_owned(bgep->genlock));
1278 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1282 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ));
1285 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data);
1289 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data)
1292 (void *)bgep, regno, data));
1294 ASSERT(mutex_owned(bgep->genlock));
1296 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1300 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE);
1304 bge_phydsp_read(bge_t *bgep, bge_regno_t regno)
1307 (void *)bgep, regno));
1309 ASSERT(mutex_owned(bgep->genlock));
1311 bge_mii_put16(bgep, MII_DSP_ADDRESS, regno);
1312 return bge_mii_get16(bgep, MII_DSP_RW_PORT);
1318 bge_phydsp_write(bge_t *bgep, bge_regno_t regno, uint16_t data)
1321 (void *)bgep, regno, data));
1323 ASSERT(mutex_owned(bgep->genlock));
1325 bge_mii_put16(bgep, MII_DSP_ADDRESS, regno);
1326 bge_mii_put16(bgep, MII_DSP_RW_PORT, data);
1352 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1357 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1362 ASSERT(mutex_owned(bgep->genlock));
1370 switch (bgep->chipid.nvtype) {
1381 bge_reg_set32(bgep, NVM_CONFIG1_REG,
1399 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1416 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp);
1417 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd);
1428 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1442 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG);
1443 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
1457 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
1479 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1484 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1489 ASSERT(mutex_owned(bgep->genlock));
1497 switch (bgep->chipid.nvtype) {
1508 bge_reg_clr32(bgep, NVM_CONFIG1_REG,
1522 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp);
1523 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr);
1524 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd);
1530 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG);
1541 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG);
1588 static void bge_nvmem_relinquish(bge_t *bgep);
1592 bge_nvmem_relinquish(bge_t *bgep)
1594 ASSERT(mutex_owned(bgep->genlock));
1596 switch (bgep->chipid.nvtype) {
1618 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1623 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
1624 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1635 static int bge_nvmem_acquire(bge_t *bgep);
1639 bge_nvmem_acquire(bge_t *bgep)
1644 ASSERT(mutex_owned(bgep->genlock));
1646 switch (bgep->chipid.nvtype) {
1698 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1699 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
1702 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1718 bge_nvmem_relinquish(bgep);
1743 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect);
1747 bge_nvmem_protect(bge_t *bgep, boolean_t protect)
1751 ASSERT(mutex_owned(bgep->genlock));
1753 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
1761 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval);
1781 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1785 if ((err = bge_nvmem_acquire(bgep)) == 0) {
1788 err = bge_seeprom_access(bgep,
1793 bge_nvmem_protect(bgep, B_FALSE);
1794 err = bge_seeprom_access(bgep,
1796 bge_nvmem_protect(bgep, B_TRUE);
1800 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1801 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1802 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1803 DEVICE_5725_SERIES_CHIPSETS(bgep) ||
1804 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1805 bge_reg_set32(bgep, NVM_ACCESS_REG,
1808 err = bge_flash_access(bgep,
1810 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1811 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1812 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1813 DEVICE_5725_SERIES_CHIPSETS(bgep) ||
1814 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1815 bge_reg_clr32(bgep, NVM_ACCESS_REG,
1821 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1822 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1823 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1824 DEVICE_5725_SERIES_CHIPSETS(bgep) ||
1825 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1826 bge_reg_set32(bgep, NVM_ACCESS_REG,
1829 bge_nvmem_protect(bgep, B_FALSE);
1830 err = bge_flash_access(bgep,
1832 bge_nvmem_protect(bgep, B_TRUE);
1833 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1834 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1835 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1836 DEVICE_5725_SERIES_CHIPSETS(bgep) ||
1837 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1838 bge_reg_clr32(bgep, NVM_ACCESS_REG,
1848 bge_nvmem_relinquish(bgep);
1856 bge_nvmem_access_cmd(bge_t *bgep, boolean_t read)
1858 switch (bgep->chipid.nvtype) {
1876 bge_nvmem_read32(bge_t *bgep, bge_regno_t addr, uint32_t *dp)
1878 return (bge_nvmem_rw32(bgep, bge_nvmem_access_cmd(bgep, B_TRUE),
1884 bge_nvmem_write32(bge_t *bgep, bge_regno_t addr, uint32_t *dp)
1886 return (bge_nvmem_rw32(bgep, bge_nvmem_access_cmd(bgep, B_FALSE),
1894 static uint64_t bge_get_nvmac(bge_t *bgep);
1898 bge_get_nvmac(bge_t *bgep)
1907 (void *)bgep));
1909 switch (bgep->chipid.nvtype) {
1926 if (DEVICE_5906_SERIES_CHIPSETS(bgep))
1931 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high))
1934 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low))
1960 static uint64_t bge_get_nvmac(bge_t *bgep);
1964 bge_get_nvmac(bge_t *bgep)
1966 _NOTE(ARGUNUSED(bgep))
1975 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep);
1979 bge_nvmem_id(bge_t *bgep)
1985 (void *)bgep));
1987 switch (bgep->chipid.device) {
2050 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG);
2071 uint32_t bge_ape_get32(bge_t *bgep, bge_regno_t regno);
2075 bge_ape_get32(bge_t *bgep, bge_regno_t regno)
2078 (void *)bgep, regno));
2080 return (ddi_get32(bgep->ape_handle, APE_ADDR(bgep, regno)));
2083 void bge_ape_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
2087 bge_ape_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
2090 (void *)bgep, regno, data));
2092 ddi_put32(bgep->ape_handle, APE_ADDR(bgep, regno), data);
2093 BGE_PCICHK(bgep);
2097 bge_ape_lock_init(bge_t *bgep)
2103 BGE_TRACE(("bge_ape_lock_init($%p)", (void *)bgep));
2105 if (bgep->chipid.device == DEVICE_ID_5761)
2120 if (!bgep->pci_func)
2123 bit = 1 << bgep->pci_func;
2125 bge_ape_put32(bgep, regbase + 4 * i, bit);
2130 bge_ape_lock(bge_t *bgep, int locknum)
2139 BGE_TRACE(("bge_ape_lock($%p, 0x%x)", (void *)bgep, locknum));
2141 if (!bgep->ape_enabled)
2146 if (bgep->chipid.device == DEVICE_ID_5761)
2150 if (!bgep->pci_func)
2153 bit = 1 << bgep->pci_func;
2165 if (bgep->chipid.device == DEVICE_ID_5761) {
2175 bge_ape_put32(bgep, req + off, bit);
2179 status = bge_ape_get32(bgep, gnt + off);
2187 bge_ape_put32(bgep, gnt + off, bit);
2195 bge_ape_unlock(bge_t *bgep, int locknum)
2200 BGE_TRACE(("bge_ape_unlock($%p, 0x%x)", (void *)bgep, locknum));
2202 if (!bgep->ape_enabled)
2207 if (bgep->chipid.device == DEVICE_ID_5761)
2211 if (!bgep->pci_func)
2214 bit = 1 << bgep->pci_func;
2226 if (bgep->chipid.device == DEVICE_ID_5761)
2231 bge_ape_put32(bgep, gnt + 4 * locknum, bit);
2236 bge_ape_event_lock(bge_t *bgep, uint32_t timeout_us)
2240 BGE_TRACE(("bge_ape_event_lock($%p, %d)", (void *)bgep, timeout_us));
2245 if (bge_ape_lock(bgep, BGE_APE_LOCK_MEM))
2248 apedata = bge_ape_get32(bgep, BGE_APE_EVENT_STATUS);
2252 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM);
2263 bge_ape_wait_for_event(bge_t *bgep, uint32_t timeout_us)
2268 BGE_TRACE(("bge_ape_wait_for_event($%p, %d)", (void *)bgep, timeout_us));
2273 apedata = bge_ape_get32(bgep, BGE_APE_EVENT_STATUS);
2285 bge_ape_scratchpad_read(bge_t *bgep, uint32_t *data, uint32_t base_off,
2296 (void *)bgep, (void*)data, base_off, lenToRead));
2298 if (!bgep->ape_has_ncsi)
2301 apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG);
2305 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS);
2309 bufoff = (bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_OFF) +
2312 maxlen = bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_LEN);
2321 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS);
2326 err = bge_ape_event_lock(bgep, 1000);
2333 bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, apedata);
2335 bge_ape_put32(bgep, bufoff, base_off);
2336 bge_ape_put32(bgep, bufoff + sizeof(uint32_t), transferLen);
2338 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM);
2339 bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1);
2343 if (bge_ape_wait_for_event(bgep, 30000))
2347 uint32_t val = bge_ape_get32(bgep, msgoff + i);
2357 bge_ape_scratchpad_write(bge_t *bgep, uint32_t dstoff, uint32_t *data,
2368 (void *)bgep, dstoff, data, lenToWrite));
2370 if (!bgep->ape_has_ncsi)
2373 apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG);
2377 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS);
2381 bufoff = (bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_OFF) +
2384 maxlen = bge_ape_get32(bgep, BGE_APE_SEG_MSG_BUF_LEN);
2396 err = bge_ape_event_lock(bgep, 1000);
2400 bge_ape_put32(bgep, bufoff, dstoff);
2401 bge_ape_put32(bgep, bufoff + sizeof(uint32_t), transferLen);
2407 bge_ape_put32(bgep, apedata, *data++);
2414 bge_ape_put32(bgep, BGE_APE_EVENT_STATUS, apedata);
2416 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM);
2417 bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1);
2424 bge_ape_send_event(bge_t *bgep, uint32_t event)
2429 BGE_TRACE(("bge_ape_send_event($%p, %d)", (void *)bgep, event));
2431 apedata = bge_ape_get32(bgep, BGE_APE_SEG_SIG);
2435 apedata = bge_ape_get32(bgep, BGE_APE_FW_STATUS);
2440 err = bge_ape_event_lock(bgep, 1000);
2444 bge_ape_put32(bgep, BGE_APE_EVENT_STATUS,
2447 bge_ape_unlock(bgep, BGE_APE_LOCK_MEM);
2448 bge_ape_put32(bgep, BGE_APE_EVENT, APE_EVENT_1);
2454 bge_ape_driver_state_change(bge_t *bgep, int mode)
2460 (void *)bgep, mode));
2462 if (!bgep->ape_enabled)
2467 bge_ape_put32(bgep, BGE_APE_HOST_SEG_SIG,
2469 bge_ape_put32(bgep, BGE_APE_HOST_SEG_LEN,
2471 apedata = bge_ape_get32(bgep, BGE_APE_HOST_INIT_COUNT);
2472 bge_ape_put32(bgep, BGE_APE_HOST_INIT_COUNT, ++apedata);
2473 bge_ape_put32(bgep, BGE_APE_HOST_DRIVER_ID,
2475 bge_ape_put32(bgep, BGE_APE_HOST_BEHAVIOR,
2477 bge_ape_put32(bgep, BGE_APE_HOST_DRVR_STATE,
2488 bge_ape_put32(bgep, BGE_APE_HOST_SEG_SIG, 0x0);
2492 bge_ape_put32(bgep, BGE_APE_HOST_WOL_SPEED,
2499 bge_ape_put32(bgep, BGE_APE_HOST_DRVR_STATE, apedata);
2512 bge_ape_send_event(bgep, event);
2519 bge_init_recv_rule(bge_t *bgep)
2521 bge_recv_rule_t *rulep = bgep->recv_rules;
2529 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
2530 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
2540 int bge_chip_id_init(bge_t *bgep);
2544 bge_chip_id_init(bge_t *bgep)
2557 cidp = &bgep->chipid;
2611 if (pci_config_get16(bgep->cfg_handle, PCI_CONF_DEVID) ==
2672 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0)
3047 if (DEVICE_5714_SERIES_CHIPSETS(bgep) ||
3048 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
3049 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
3074 cidp->nvtype = bge_nvmem_id(bgep);
3087 bge_problem(bgep,
3091 bge_problem(bgep,
3098 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
3105 bge_chip_msi_trig(bge_t *bgep)
3109 regval = bgep->param_msi_cnt<<4;
3110 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval);
3134 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
3139 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
3146 (void *)bgep, regno, mask, val));
3149 regval = bge_reg_get32(bgep, regno);
3155 bge_problem(bgep, "bge_chip_poll_engine failed: regno = 0x%lx", regno);
3156 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
3176 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno);
3180 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno)
3187 regval = bge_reg_get32(bgep, regno);
3190 (void *)bgep, regno));
3205 if (DEVICE_5705_SERIES_CHIPSETS(bgep) ||
3206 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
3207 DEVICE_5725_SERIES_CHIPSETS(bgep) ||
3208 DEVICE_5721_SERIES_CHIPSETS(bgep) ||
3209 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
3210 DEVICE_5714_SERIES_CHIPSETS(bgep) ||
3211 DEVICE_5906_SERIES_CHIPSETS(bgep)) {
3213 if (bgep->chipid.pci_type == BGE_PCI_E) {
3214 if (bgep->chipid.asic_rev ==
3216 bgep->chipid.asic_rev ==
3218 bgep->chipid.asic_rev ==
3220 val32 = bge_reg_get32(bgep,
3224 bge_reg_put32(bgep,
3228 (bgep->cfg_handle,
3231 pci_config_put32(bgep->cfg_handle,
3234 bge_reg_set32(bgep, regno,
3251 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval);
3260 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
3261 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET);
3263 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF);
3266 if (bgep->chipid.pci_type == BGE_PCI_E) {
3274 mhcr = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR);
3275 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR,
3279 if ((bgep->chipid.chip_label == 5721) ||
3280 (bgep->chipid.chip_label == 5751) ||
3281 (bgep->chipid.chip_label == 5752) ||
3282 (bgep->chipid.chip_label == 5789) ||
3283 (bgep->chipid.chip_label == 5906)) {
3284 pci_config_put16(bgep->cfg_handle,
3286 pci_config_put16(bgep->cfg_handle,
3290 if ((bgep->chipid.chip_label == 5723) ||
3291 (bgep->chipid.chip_label == 5761)) {
3292 pci_config_put16(bgep->cfg_handle,
3294 pci_config_put16(bgep->cfg_handle,
3298 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
3299 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
3300 val16 = pci_config_get16(bgep->cfg_handle,
3304 pci_config_put16(bgep->cfg_handle,
3309 BGE_PCICHK(bgep);
3313 bge_reg_put32(bgep, regno, regval);
3314 return (bge_chip_poll_engine(bgep, regno,
3329 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno,
3334 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
3339 (void *)bgep, regno, morebits));
3348 if (bgep->asf_enabled)
3357 bge_reg_put32(bgep, regno, ~(uint32_t)0);
3359 bge_reg_put32(bgep, regno, 0);
3363 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3378 regval = bge_reg_get32(bgep, regno);
3381 bge_reg_put32(bgep, regno, regval);
3383 return bge_chip_poll_engine(bgep, regno, STATE_MACHINE_ENABLE_BIT, 0);
3396 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno,
3401 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
3406 (void *)bgep, regno, morebits));
3412 if (bgep->asf_enabled)
3421 bge_reg_put32(bgep, regno, ~(uint32_t)0);
3423 bge_reg_put32(bgep, regno, 0);
3427 regval = bge_reg_get32(bgep, regno);
3430 bge_reg_put32(bgep, regno, regval);
3431 return (bge_chip_poll_engine(bgep, regno,
3440 void bge_sync_mac_modes(bge_t *bgep);
3444 bge_sync_mac_modes(bge_t *bgep)
3449 ASSERT(mutex_owned(bgep->genlock));
3454 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
3457 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
3458 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) {
3459 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
3460 DEVICE_5725_SERIES_CHIPSETS(bgep) ||
3461 DEVICE_5714_SERIES_CHIPSETS(bgep))
3465 } else if (bgep->param_link_speed == 10 ||
3466 bgep->param_link_speed == 100)
3470 if (bgep->param_link_duplex == LINK_DUPLEX_HALF)
3474 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC)
3478 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
3480 (void *)bgep, regval, macmode));
3485 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
3486 if (bgep->param_link_tx_pause)
3490 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode);
3492 (void *)bgep, regval, macmode));
3497 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG);
3498 if (bgep->param_link_rx_pause)
3502 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode);
3504 (void *)bgep, regval, macmode));
3510 if (bgep->chipid.device == DEVICE_ID_5785)
3511 if (bgep->param_link_speed == 10)
3512 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK
3515 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
3524 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
3526 int bge_chip_sync(bge_t *bgep);
3532 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive)
3534 bge_chip_sync(bge_t *bgep)
3537 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits);
3545 (void *)bgep));
3547 ASSERT(mutex_owned(bgep->genlock));
3552 if (bgep->promisc)
3573 if (!bgep->asf_enabled) {
3574 if (!bge_chip_disable_engine(bgep,
3578 if (!bge_chip_disable_engine(bgep,
3583 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG,
3587 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3589 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG))
3597 bge_reg_put32(bgep, MAC_HASH_REG(i), 0);
3600 bge_reg_put32(bgep, MAC_HASH_REG(i),
3601 bgep->mcast_hash[i] | fill);
3604 if (!bgep->asf_enabled || !asf_keeplive) {
3615 macaddr |= bgep->curr_addr[j].addr[i];
3618 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr);
3622 (void *)bgep, macaddr));
3634 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill);
3640 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS);
3645 bge_sync_mac_modes(bgep);
3650 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) {
3651 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3654 if (!bgep->asf_enabled) {
3655 if (!bge_chip_enable_engine(bgep,
3659 if (!bge_chip_enable_engine(bgep,
3664 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3680 void bge_chip_stop_nonblocking(bge_t *bgep);
3688 bge_chip_stop_nonblocking(bge_t *bgep)
3695 bgep->progress &= ~PROGRESS_READY;
3699 (void) bge_chip_disable_engine(bgep, *rbp, 0);
3703 bgep->bge_chip_state = BGE_CHIP_STOPPED;
3715 void bge_chip_stop(bge_t *bgep, boolean_t fault);
3719 bge_chip_stop(bge_t *bgep, boolean_t fault)
3726 (void *)bgep));
3728 ASSERT(mutex_owned(bgep->genlock));
3730 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR,
3731 (pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR) |
3734 ok &= bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 0);
3735 ok &= bge_chip_disable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 0);
3736 ok &= bge_chip_disable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0);
3737 ok &= bge_chip_disable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 0);
3738 ok &= bge_chip_disable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 0);
3739 ok &= bge_chip_disable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 0);
3740 ok &= bge_chip_disable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 0);
3742 ok &= bge_chip_disable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 0);
3743 ok &= bge_chip_disable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 0);
3744 ok &= bge_chip_disable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0);
3745 ok &= bge_chip_disable_engine(bgep, READ_DMA_MODE_REG, 0);
3746 ok &= bge_chip_disable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0);
3747 ok &= bge_chip_disable_engine(bgep, DMA_COMPLETION_MODE_REG, 0);
3748 ok &= bge_chip_disable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 0);
3749 ok &= bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0);
3751 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_ENABLE_TDE);
3754 ok &= bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, 0);
3755 ok &= bge_chip_disable_engine(bgep, WRITE_DMA_MODE_REG, 0);
3756 ok &= bge_chip_disable_engine(bgep, MBUF_CLUSTER_FREE_MODE_REG, 0);
3757 ok &= bge_chip_disable_engine(bgep, FTQ_RESET_REG, 0);
3758 ok &= bge_chip_disable_engine(bgep, BUFFER_MANAGER_MODE_REG, 0);
3759 ok &= bge_chip_disable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0);
3760 ok &= bge_chip_disable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0);
3763 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
3768 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
3769 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0);
3776 if (bgep->bge_chip_state != BGE_CHIP_FAULT) {
3777 bgep->bge_chip_state = BGE_CHIP_FAULT;
3778 if (!bgep->manual_reset)
3779 ddi_fm_service_impact(bgep->devinfo,
3781 if (bgep->bge_dma_error) {
3787 if (bgep->progress & PROGRESS_KSTATS) {
3788 bge_fini_kstats(bgep);
3789 bgep->progress &= ~PROGRESS_KSTATS;
3791 if (bgep->progress & PROGRESS_INTR) {
3792 bge_intr_disable(bgep);
3793 rw_enter(bgep->errlock, RW_WRITER);
3794 bge_fini_rings(bgep);
3795 rw_exit(bgep->errlock);
3796 bgep->progress &= ~PROGRESS_INTR;
3798 if (bgep->progress & PROGRESS_BUFS) {
3799 bge_free_bufs(bgep);
3800 bgep->progress &= ~PROGRESS_BUFS;
3802 bgep->bge_dma_error = B_FALSE;
3806 bgep->bge_chip_state = BGE_CHIP_STOPPED;
3813 static uint64_t bge_poll_firmware(bge_t *bgep);
3817 bge_poll_firmware(bge_t *bgep)
3847 if (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5906) {
3850 val = bge_reg_get32(bgep, VCPU_STATUS_REG);
3855 (void *)bgep, i));
3856 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3860 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32;
3861 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep))
3863 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3865 if (!bgep->asf_enabled) {
3874 if (bgep->bge_chip_state != BGE_CHIP_INITIAL)
3879 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM);
3881 (void *)bgep, gen, i));
3895 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
3897 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
3903 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode)
3905 bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
3922 (void *)bgep, enable_dma));
3924 ASSERT(mutex_owned(bgep->genlock));
3927 (void *)bgep, enable_dma, bgep->bge_chip_state));
3932 switch (bgep->bge_chip_state) {
3945 bge_chip_stop(bgep, B_FALSE);
3957 if (bgep->asf_enabled) {
3963 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3965 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3966 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) |
3970 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
3972 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET);
3988 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3996 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3999 if (bgep->asf_enabled)
4000 bgep->asf_wordswapped = B_FALSE;
4006 if (bge_nvmem_acquire(bgep) != EAGAIN)
4010 bgep->ifname));
4012 bge_ape_lock(bgep, BGE_APE_LOCK_GRC);
4015 if (!bgep->asf_enabled) {
4018 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic);
4023 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4024 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
4025 bge_reg_set32(bgep, FAST_BOOT_PC, 0);
4026 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
4035 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
4037 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG))
4040 bge_chip_cfg_init(bgep, &chipid, enable_dma);
4046 if ((bgep->chipid.chip_label == 5721) ||
4047 (bgep->chipid.chip_label == 5751) ||
4048 (bgep->chipid.chip_label == 5752) ||
4049 (bgep->chipid.chip_label == 5755) ||
4050 (bgep->chipid.chip_label == 5756) ||
4051 (bgep->chipid.chip_label == 5789) ||
4052 (bgep->chipid.chip_label == 5906))
4053 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
4059 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
4076 if (bgep->asf_enabled)
4079 bge_reg_put32(bgep, MODE_CONTROL_REG, tmp);
4082 if (bgep->asf_enabled) {
4084 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
4086 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG));
4090 if (!bgep->asf_newhandshake) {
4093 bge_asf_post_reset_old_mode(bgep,
4096 bge_asf_post_reset_old_mode(bgep,
4105 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX);
4111 mailbox = bge_nic_get32(bgep,
4117 if (!bgep->asf_newhandshake) {
4121 bge_asf_post_reset_old_mode(bgep,
4124 bge_asf_post_reset_old_mode(bgep,
4132 bge_ape_unlock(bgep, BGE_APE_LOCK_GRC);
4137 mac = bge_poll_firmware(bgep);
4139 if (bgep->chipid.device == DEVICE_ID_5720) {
4140 tmp = bge_reg_get32(bgep, CPMU_CLCK_ORIDE_REG);
4141 bge_reg_put32(bgep, CPMU_CLCK_ORIDE_REG,
4159 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG,
4160 bgep->chipid.bge_mlcr_default);
4162 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
4163 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
4164 tmp = bge_reg_get32(bgep, SERDES_RX_CONTROL);
4166 bge_reg_put32(bgep, SERDES_RX_CONTROL, tmp);
4169 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
4174 if (bgep->ape_enabled)
4175 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG,
4178 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
4191 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ,
4192 bgep->chipid.clsize);
4193 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER,
4194 bgep->chipid.latency);
4195 bge_reg_put32(bgep, PCI_CONF_SUBVENID,
4196 (bgep->chipid.subdev << 16) | bgep->chipid.subven);
4203 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0));
4205 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET"));
4206 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE);
4211 if (bgep->intr_type == DDI_INTR_TYPE_MSI)
4212 bge_reg_set32(bgep, MSI_MODE_REG,
4223 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) {
4225 mac = bge_get_nvmac(bgep);
4227 bgep->chipid.hw_mac_addr = mac;
4229 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac;
4232 bgep->chipid.vendor_addr.set = B_TRUE;
4237 if (bgep->asf_enabled && bgep->asf_newhandshake) {
4242 bge_asf_post_reset_new_mode(bgep,
4245 bge_asf_post_reset_new_mode(bgep,
4255 bgep->chip_resets += 1;
4256 bgep->bge_chip_state = BGE_CHIP_RESET;
4264 int bge_chip_start(bge_t *bgep, boolean_t reset_phys);
4268 bge_chip_coalesce_update(bge_t *bgep)
4270 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG,
4271 bgep->chipid.tx_count_norm);
4272 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG,
4273 bgep->chipid.tx_ticks_norm);
4274 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG,
4275 bgep->chipid.rx_count_norm);
4276 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG,
4277 bgep->chipid.rx_ticks_norm);
4281 bge_chip_start(bge_t *bgep, boolean_t reset_phys)
4297 (void *)bgep));
4299 ASSERT(mutex_owned(bgep->genlock));
4300 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET);
4303 bge_eee_init(bgep);
4305 if (bgep->ape_enabled) {
4310 regval = pci_config_get32(bgep->cfg_handle,
4314 pci_config_put32(bgep->cfg_handle,
4329 if (bgep->chipid.statistic_type == BGE_STAT_BLK)
4330 bge_nic_zero(bgep, NIC_MEM_STATISTICS,
4336 DMA_ZERO(bgep->status_block);
4341 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR,
4342 bgep->chipid.bge_dma_rwctrl);
4349 bge_reg_set32(bgep, MODE_CONTROL_REG,
4353 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4354 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
4355 reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)
4357 regval = bge_reg_get32(bgep, reg);
4358 if ((bgep->chipid.device == DEVICE_ID_5719) ||
4359 (bgep->chipid.device == DEVICE_ID_5720) ||
4360 (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)) {
4369 bge_reg_put32(bgep, reg,
4372 if ((CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5719) ||
4373 (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5720) ||
4374 (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)) {
4375 reg = (CHIP_ASIC_REV(bgep) == CHIP_ASIC_REV_5762)
4377 regval = bge_reg_get32(bgep, reg);
4378 bge_reg_put32(bgep, reg, (regval |
4390 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM)
4391 bge_reg_set32(bgep, MODE_CONTROL_REG,
4400 regval = bge_reg_get32(bgep, MISC_CONFIG_REG);
4402 bge_reg_put32(bgep, MISC_CONFIG_REG, regval);
4404 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
4407 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ);
4408 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */
4420 if ((bgep->chipid.mbuf_length != 0) &&
4421 (DEVICE_5704_SERIES_CHIPSETS(bgep))) {
4422 bge_reg_put32(bgep, MBUF_POOL_BASE_REG,
4423 bgep->chipid.mbuf_base);
4424 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG,
4425 bgep->chipid.mbuf_length);
4426 bge_reg_put32(bgep, DMAD_POOL_BASE_REG,
4428 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG,
4435 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG,
4436 bgep->chipid.mbuf_lo_water_rdma);
4437 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG,
4438 bgep->chipid.mbuf_lo_water_rmac);
4439 bge_reg_put32(bgep, MBUF_HIWAT_REG,
4440 bgep->chipid.mbuf_hi_water);
4445 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4446 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG,
4448 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG,
4451 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
4457 if (bgep->chipid.device == DEVICE_ID_5719)
4459 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4460 DEVICE_5725_SERIES_CHIPSETS(bgep))
4462 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, regval))
4465 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0))
4471 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4472 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
4473 buff_ring_t *brp = &bgep->buff[BGE_STD_BUFF_RING];
4474 bge_reg_put64(bgep, STD_RCV_BD_RING_RCB_REG,
4476 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8,
4478 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc,
4481 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG,
4482 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb);
4484 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4485 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
4486 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb);
4487 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG,
4488 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb);
4494 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
4495 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4496 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
4498 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
4506 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4511 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0);
4512 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0);
4513 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring),
4514 &bgep->send[ring].hw_rcb);
4521 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4526 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring),
4527 &bgep->recv[ring].hw_rcb);
4532 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0);
4533 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4534 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0);
4535 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0);
4543 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE)
4545 if (bge_chip_sync(bgep) == DDI_FAILURE)
4552 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ;
4553 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu);
4558 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
4563 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
4569 bge_reg_put32(bgep, RCV_LP_CONFIG_REG,
4570 RCV_LP_CONFIG(bgep->chipid.rx_rings));
4571 switch (MHCR_CHIP_ASIC_REV(bgep)) {
4576 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
4581 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG);
4583 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask);
4586 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE);
4588 if (bgep->chipid.rx_rings > 1)
4589 bge_init_recv_rule(bgep);
4594 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
4595 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4596 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
4599 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
4605 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0))
4611 bge_chip_coalesce_update(bgep);
4612 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4613 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG,
4615 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG,
4617 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG,
4619 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG,
4629 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG,
4630 bgep->status_block.cookie.dmac_laddress);
4636 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4637 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG,
4638 bgep->statistics.cookie.dmac_laddress);
4639 bge_reg_put32(bgep, STATISTICS_TICKS_REG,
4641 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG,
4643 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG,
4654 if (bgep->chipid.device == DEVICE_ID_5719) {
4656 if (bge_reg_get32(bgep, (BGE_RDMA_LENGTH + (i << 2))) >
4657 bgep->chipid.default_mtu)
4661 regval = bge_reg_get32(bgep, RDMA_CORR_CTRL_REG);
4663 bge_reg_put32(bgep, RDMA_CORR_CTRL_REG, regval);
4664 bgep->rdma_length_bug_on_5719 = B_TRUE;
4668 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS &&
4669 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS)
4673 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4674 DEVICE_5725_SERIES_CHIPSETS(bgep))
4676 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode))
4678 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG,
4681 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0))
4684 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4685 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG,
4693 if (bgep->ape_enabled) {
4695 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG,
4698 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4702 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4710 if (bgep->ape_enabled) {
4712 bge_ape_put32(bgep, BGE_APE_HOST_HEARTBEAT_INT_MS,
4723 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0);
4737 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4738 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0))
4743 if ((MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5755) ||
4744 (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5723) ||
4745 (MHCR_CHIP_ASIC_REV(bgep) == MHCR_CHIP_ASIC_REV_5906)) {
4748 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
4754 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
4755 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4756 DEVICE_5725_SERIES_CHIPSETS(bgep))
4758 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
4764 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
4767 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4768 if (!bge_chip_enable_engine(bgep,
4771 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0))
4773 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG,
4776 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG,
4779 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG,
4782 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0))
4784 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG,
4787 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG,
4798 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
4801 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, regval))
4807 if (!bgep->asf_enabled) {
4808 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4812 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0))
4816 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4826 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT);
4833 switch (bgep->chipid.device) {
4847 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
4852 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
4860 if (bge_phys_update(bgep) == DDI_FAILURE)
4863 bge_phys_check(bgep);
4864 bgep->link_state = (bgep->param_link_up) ? LINK_STATE_UP :
4866 bge_sync_mac_modes(bgep);
4867 mac_link_update(bgep->mh, bgep->link_state);
4874 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg,
4875 bgep->buff[ring].rf_next);
4881 if (bgep->intr_type == DDI_INTR_TYPE_MSI)
4882 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70);
4891 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG,
4895 if (bgep->asf_enabled) {
4896 bge_reg_set32(bgep, MODE_CONTROL_REG,
4903 bge_reg_set32(bgep, MODE_CONTROL_REG,
4911 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
4912 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
4913 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5717,
4916 mhcr = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR);
4917 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR,
4925 if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
4926 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR,
4927 bgep->chipid.mask_pci_int);
4932 bgep->bge_chip_state = BGE_CHIP_RUNNING;
4950 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags);
4954 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags)
4960 (void *)bgep, bits));
4962 ASSERT(bgep->bge_guard == BGE_GUARD);
4964 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL);
4965 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl);
4969 bsp = DMA_VPTR(bgep->status_block);
4973 (void *)bgep, bits, *flags));
4978 void bge_wake_factotum(bge_t *bgep);
4982 bge_wake_factotum(bge_t *bgep)
4984 mutex_enter(bgep->softintrlock);
4985 if (bgep->factotum_flag == 0) {
4986 bgep->factotum_flag = 1;
4987 ddi_trigger_softintr(bgep->factotum_id);
4989 mutex_exit(bgep->softintrlock);
4993 bge_intr_error_handler(bge_t *bgep)
5005 ASSERT(mutex_owned(bgep->genlock));
5011 flow = bge_reg_get32(bgep, FLOW_ATTN_REG);
5012 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG);
5013 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG);
5014 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
5015 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG);
5016 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG);
5017 emac = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG);
5018 msis = bge_reg_get32(bgep, MSI_STATUS_REG);
5019 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
5020 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG);
5023 (void *)bgep, flow, rdma, wdma, emac, msis));
5025 (void *)bgep, tmac, rmac, rxrs, txrs));
5030 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
5031 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0);
5032 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0);
5033 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0);
5034 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0);
5035 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0);
5036 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0);
5048 bge_t *bgep = (void *)arg1; /* private device info */
5062 ASSERT(bgep->progress & PROGRESS_HWINT);
5065 mutex_enter(bgep->genlock);
5067 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
5075 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
5076 if (!(DEVICE_5717_SERIES_CHIPSETS(bgep) ||
5077 DEVICE_5725_SERIES_CHIPSETS(bgep)) &&
5079 if (bge_check_acc_handle(bgep, bgep->io_handle)
5082 mutex_exit(bgep->genlock);
5089 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR,
5090 bgep->chipid.mask_pci_int);
5096 regval = bge_reg_get32(bgep, MSI_STATUS_REG);
5098 BGE_REPORT((bgep, "msi error attention,"
5100 bge_reg_put32(bgep, MSI_STATUS_REG, regval);
5115 bgep->missed_dmas += 1;
5116 bsp = DMA_VPTR(bgep->status_block);
5118 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) {
5124 (void) bge_check_acc_handle(bgep,
5125 bgep->io_handle);
5126 mutex_exit(bgep->genlock);
5130 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED |
5133 bgep->bge_dma_error = B_TRUE;
5143 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
5145 if (bge_check_acc_handle(bgep, bgep->io_handle) !=
5151 if (bge_phys_check(bgep)) {
5152 bgep->link_state = bgep->param_link_up ?
5154 bge_sync_mac_modes(bgep);
5155 mac_link_update(bgep->mh, bgep->link_state);
5158 if (bge_check_acc_handle(bgep, bgep->io_handle) !=
5164 bge_intr_error_handler(bgep);
5166 if (bge_check_acc_handle(bgep, bgep->io_handle) !=
5176 bgep->bge_intr_running = B_TRUE;
5177 mutex_exit(bgep->genlock);
5178 bge_receive(bgep, bsp);
5179 (void) bge_recycle(bgep, bsp);
5180 mutex_enter(bgep->genlock);
5181 bgep->bge_intr_running = B_FALSE;
5194 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
5196 if (bgep->chipid.pci_type == BGE_PCI_E)
5197 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG);
5198 bgep->missed_dmas = 0;
5201 if (bgep->missed_dmas) {
5209 BGE_REPORT((bgep, "interrupt: flags 0x%llx - "
5211 bgep->missed_updates++;
5212 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG,
5215 if (bgep->missed_dmas >= bge_dma_miss_limit) {
5228 bge_fm_ereport(bgep,
5237 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
5238 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR,
5239 bgep->chipid.mask_pci_int);
5240 if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
5245 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5248 mutex_exit(bgep->genlock);
5254 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) {
5261 bge_asf_update_status(bgep);
5262 bge_asf_stop_timer(bgep);
5263 bgep->asf_status = ASF_STAT_STOP;
5265 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
5266 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
5269 bge_chip_stop(bgep, B_TRUE);
5270 (void) bge_check_acc_handle(bgep, bgep->io_handle);
5271 mutex_exit(bgep->genlock);
5285 static boolean_t bge_factotum_stall_check(bge_t *bgep);
5289 bge_factotum_stall_check(bge_t *bgep)
5295 if ((now - bgep->timestamp) < BGE_CYCLIC_PERIOD)
5298 bgep->timestamp = now;
5300 ASSERT(mutex_owned(bgep->genlock));
5316 dogval = bge_atomic_shl32(&bgep->watchdog, 1);
5317 bsp = DMA_VPTR(bgep->status_block);
5318 if (dogval < bge_watchdog_count || bge_recycle(bgep, bsp))
5322 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval));
5324 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL);
5339 bge_t *bgep;
5344 bgep = (void *)arg;
5346 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep));
5348 mutex_enter(bgep->softintrlock);
5349 if (bgep->factotum_flag == 0) {
5350 mutex_exit(bgep->softintrlock);
5353 bgep->factotum_flag = 0;
5354 mutex_exit(bgep->softintrlock);
5359 mutex_enter(bgep->genlock);
5360 switch (bgep->bge_chip_state) {
5366 if (bgep->chipid.device == DEVICE_ID_5700) {
5367 if (bge_phys_check(bgep)) {
5368 bgep->link_state = (bgep->param_link_up) ?
5370 bge_sync_mac_modes(bgep);
5371 mac_link_update(bgep->mh, bgep->link_state);
5375 error = bge_factotum_stall_check(bgep);
5377 bgep->bge_dma_error = B_TRUE;
5380 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5383 bgep->bge_chip_state = BGE_CHIP_ERROR;
5395 if (!(bgep->progress & PROGRESS_BUFS)) {
5400 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) {
5401 mutex_exit(bgep->genlock);
5404 bgep->progress |= PROGRESS_BUFS;
5406 if (!(bgep->progress & PROGRESS_INTR)) {
5407 bge_init_rings(bgep);
5408 bge_intr_enable(bgep);
5409 bgep->progress |= PROGRESS_INTR;
5411 if (!(bgep->progress & PROGRESS_KSTATS)) {
5412 bge_init_kstats(bgep,
5413 ddi_get_instance(bgep->devinfo));
5414 bgep->progress |= PROGRESS_KSTATS;
5417 BGE_REPORT((bgep, "automatic recovery activated"));
5419 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) {
5420 bgep->bge_chip_state = BGE_CHIP_ERROR;
5423 if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
5425 bgep->bge_chip_state = BGE_CHIP_ERROR;
5428 if (bge_check_acc_handle(bgep, bgep->io_handle) !=
5430 bgep->bge_chip_state = BGE_CHIP_ERROR;
5435 if (bgep->asf_enabled &&
5436 bgep->asf_status != ASF_STAT_RUN) {
5437 bgep->asf_timeout_id = timeout(
5438 bge_asf_heartbeat, (void *)bgep,
5441 bgep->asf_status = ASF_STAT_RUN;
5444 if (!bgep->manual_reset) {
5445 ddi_fm_service_impact(bgep->devinfo,
5461 if (error && !bgep->bge_intr_running) {
5463 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) {
5469 bge_asf_update_status(bgep);
5470 bge_asf_stop_timer(bgep);
5471 bgep->asf_status = ASF_STAT_STOP;
5473 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
5474 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
5477 bge_chip_stop(bgep, B_TRUE);
5478 (void) bge_check_acc_handle(bgep, bgep->io_handle);
5480 mutex_exit(bgep->genlock);
5498 bge_t *bgep;
5501 bgep = arg;
5503 switch (bgep->bge_chip_state) {
5510 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW);
5511 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5512 ddi_fm_service_impact(bgep->devinfo,
5523 mutex_enter(bgep->genlock);
5525 if (bgep->eee_lpi_wait && !--bgep->eee_lpi_wait) {
5527 bge_eee_enable(bgep);
5530 if (bgep->rdma_length_bug_on_5719) {
5531 if ((bge_reg_get32(bgep, STAT_IFHCOUT_UPKGS_REG) +
5532 bge_reg_get32(bgep, STAT_IFHCOUT_MPKGS_REG) +
5533 bge_reg_get32(bgep, STAT_IFHCOUT_BPKGS_REG)) >
5535 regval = bge_reg_get32(bgep, RDMA_CORR_CTRL_REG);
5537 bge_reg_put32(bgep, RDMA_CORR_CTRL_REG, regval);
5538 bgep->rdma_length_bug_on_5719 = B_FALSE;
5542 mutex_exit(bgep->genlock);
5544 bge_wake_factotum(bgep);
5558 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
5562 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
5568 (void *)bgep, (void *)ppd));
5574 regval = pci_config_get8(bgep->cfg_handle, regno);
5578 regval = pci_config_get16(bgep->cfg_handle, regno);
5582 regval = pci_config_get32(bgep->cfg_handle, regno);
5586 regval = pci_config_get64(bgep->cfg_handle, regno);
5593 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
5597 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
5603 (void *)bgep, (void *)ppd));
5610 pci_config_put8(bgep->cfg_handle, regno, regval);
5614 pci_config_put16(bgep->cfg_handle, regno, regval);
5618 pci_config_put32(bgep->cfg_handle, regno, regval);
5622 pci_config_put64(bgep->cfg_handle, regno, regval);
5627 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd);
5631 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd)
5637 (void *)bgep, (void *)ppd));
5639 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
5643 regval = ddi_get8(bgep->io_handle, regaddr);
5647 regval = ddi_get16(bgep->io_handle, regaddr);
5651 regval = ddi_get32(bgep->io_handle, regaddr);
5655 regval = ddi_get64(bgep->io_handle, regaddr);
5662 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd);
5666 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd)
5672 (void *)bgep, (void *)ppd));
5674 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
5679 ddi_put8(bgep->io_handle, regaddr, regval);
5683 ddi_put16(bgep->io_handle, regaddr, regval);
5687 ddi_put32(bgep->io_handle, regaddr, regval);
5691 ddi_put64(bgep->io_handle, regaddr, regval);
5694 BGE_PCICHK(bgep);
5697 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5701 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5708 (void *)bgep, (void *)ppd));
5711 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5714 regaddr = PIO_ADDR(bgep, regoff);
5718 regval = ddi_get8(bgep->io_handle, regaddr);
5722 regval = ddi_get16(bgep->io_handle, regaddr);
5726 regval = ddi_get32(bgep->io_handle, regaddr);
5730 regval = ddi_get64(bgep->io_handle, regaddr);
5737 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5741 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5748 (void *)bgep, (void *)ppd));
5751 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5754 regaddr = PIO_ADDR(bgep, regoff);
5759 ddi_put8(bgep->io_handle, regaddr, regval);
5763 ddi_put16(bgep->io_handle, regaddr, regval);
5767 ddi_put32(bgep->io_handle, regaddr, regval);
5771 ddi_put64(bgep->io_handle, regaddr, regval);
5774 BGE_PCICHK(bgep);
5777 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5781 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5784 (void *)bgep, (void *)ppd));
5786 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2);
5789 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5793 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5796 (void *)bgep, (void *)ppd));
5798 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
5803 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5807 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5813 (void *)bgep, (void *)ppd));
5815 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data);
5819 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5823 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5828 (void *)bgep, (void *)ppd));
5831 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data);
5837 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5841 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5847 (void *)bgep, (void *)ppd));
5849 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data);
5853 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5857 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5862 (void *)bgep, (void *)ppd));
5865 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE,
5870 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5874 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5880 (void *)bgep, (void *)ppd));
5903 (void *)bgep, (void *)ppd, regval, vaddr));
5908 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5912 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5918 (void *)bgep, (void *)ppd));
5924 (void *)bgep, (void *)ppd, regval, vaddr));
5945 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5950 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5952 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd);
5963 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd);
6073 mem_va = (uintptr_t)bgep;
6074 maxoff = sizeof (*bgep);
6089 areap = &bgep->tx_desc;
6092 areap = &bgep->tx_buff[0];
6095 areap = &bgep->rx_desc[0];
6098 areap = &bgep->rx_buff[0];
6101 areap = &bgep->status_block;
6104 if (bgep->chipid.statistic_type == BGE_STAT_BLK)
6105 areap = &bgep->statistics;
6142 (*ppfn)(bgep, ppd);
6146 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
6151 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
6153 ASSERT(mutex_owned(bgep->genlock));
6158 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd);
6169 return (bge_pp_ioctl(bgep, cmd, mp, iocp));
6179 bgep->bge_chip_state = BGE_CHIP_FAULT;
6180 ddi_trigger_softintr(bgep->factotum_id);
6181 (void) bge_restart(bgep, cmd == BGE_HARD_RESET);
6190 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
6195 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
6217 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd);
6221 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg);
6225 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data);
6234 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
6239 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
6261 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd);
6266 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
6278 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
6283 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
6305 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd);
6310 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
6320 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
6325 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
6330 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp));
6332 ASSERT(mutex_owned(bgep->genlock));
6338 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd);
6348 return (bge_diag_ioctl(bgep, cmd, mp, iocp));
6355 return (bge_mii_ioctl(bgep, cmd, mp, iocp));
6360 return (bge_see_ioctl(bgep, cmd, mp, iocp));
6366 return (bge_flash_ioctl(bgep, cmd, mp, iocp));
6378 bge_t *bgep = rrp->bgep;
6380 mutex_enter(bgep->genlock);
6389 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks);
6390 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count);
6392 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
6393 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
6394 mutex_exit(bgep->genlock);
6400 bge_nic_read32(bge_t *bgep, bge_regno_t addr)
6405 if (!bgep->asf_wordswapped) {
6413 if (DEVICE_5717_SERIES_CHIPSETS(bgep) ||
6414 DEVICE_5725_SERIES_CHIPSETS(bgep)) {
6419 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
6420 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR);
6421 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
6426 (void *)bgep, addr, data));
6432 bge_asf_update_status(bge_t *bgep)
6436 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE);
6437 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4);
6438 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3);
6440 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
6441 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
6458 bge_t *bgep = (bge_t *)arg;
6460 mutex_enter(bgep->genlock);
6461 bge_asf_update_status((bge_t *)bgep);
6462 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
6463 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
6464 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK)
6465 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
6466 mutex_exit(bgep->genlock);
6467 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep,
6473 bge_asf_stop_timer(bge_t *bgep)
6477 while ((bgep->asf_timeout_id != 0) &&
6478 (tmp_id != bgep->asf_timeout_id)) {
6479 tmp_id = bgep->asf_timeout_id;
6482 bgep->asf_timeout_id = 0;
6491 bge_asf_get_config(bge_t *bgep)
6496 bgep->asf_enabled = B_FALSE;
6499 if (bgep->ape_enabled)
6502 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR);
6504 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR);
6511 bgep->asf_enabled = B_TRUE;
6513 bgep->asf_enabled = B_FALSE;
6515 bgep->asf_enabled = B_FALSE;
6520 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode)
6525 ASSERT(bgep->asf_enabled);
6528 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW);
6529 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
6530 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
6532 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
6537 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
6540 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX,
6543 if (bgep->asf_newhandshake) {
6546 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6550 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6554 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6564 bge_ape_driver_state_change(bgep, mode);
6569 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode)
6573 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6577 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6581 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6591 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode)
6595 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6599 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6607 bge_ape_driver_state_change(bgep, mode);