Lines Matching defs:bge_reg_put32
613 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
614 #pragma inline(bge_reg_put32)
617 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
619 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)",
639 bge_reg_put32(bgep, regno, regval);
655 bge_reg_put32(bgep, regno, regval);
1191 bge_reg_put32(bgep, MI_COMMS_REG, cmd);
1416 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp);
1417 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd);
1443 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
1522 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp);
1523 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr);
1524 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd);
1623 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
1699 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
1761 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval);
2529 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
2530 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
3224 bge_reg_put32(bgep,
3313 bge_reg_put32(bgep, regno, regval);
3357 bge_reg_put32(bgep, regno, ~(uint32_t)0);
3359 bge_reg_put32(bgep, regno, 0);
3381 bge_reg_put32(bgep, regno, regval);
3421 bge_reg_put32(bgep, regno, ~(uint32_t)0);
3423 bge_reg_put32(bgep, regno, 0);
3430 bge_reg_put32(bgep, regno, regval);
3478 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
3490 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode);
3502 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode);
3512 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK
3515 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
3597 bge_reg_put32(bgep, MAC_HASH_REG(i), 0);
3600 bge_reg_put32(bgep, MAC_HASH_REG(i),
3634 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill);
3768 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
3769 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0);
3965 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
4079 bge_reg_put32(bgep, MODE_CONTROL_REG, tmp);
4084 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
4141 bge_reg_put32(bgep, CPMU_CLCK_ORIDE_REG,
4159 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG,
4166 bge_reg_put32(bgep, SERDES_RX_CONTROL, tmp);
4175 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG,
4178 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
4195 bge_reg_put32(bgep, PCI_CONF_SUBVENID,
4270 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG,
4272 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG,
4274 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG,
4276 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG,
4369 bge_reg_put32(bgep, reg,
4378 bge_reg_put32(bgep, reg, (regval |
4402 bge_reg_put32(bgep, MISC_CONFIG_REG, regval);
4422 bge_reg_put32(bgep, MBUF_POOL_BASE_REG,
4424 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG,
4426 bge_reg_put32(bgep, DMAD_POOL_BASE_REG,
4428 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG,
4435 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG,
4437 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG,
4439 bge_reg_put32(bgep, MBUF_HIWAT_REG,
4446 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG,
4448 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG,
4451 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
4476 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8,
4478 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc,
4494 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
4496 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
4498 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
4553 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu);
4558 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
4563 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
4569 bge_reg_put32(bgep, RCV_LP_CONFIG_REG,
4576 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
4583 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask);
4594 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
4596 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
4599 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
4613 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG,
4615 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG,
4617 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG,
4619 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG,
4639 bge_reg_put32(bgep, STATISTICS_TICKS_REG,
4641 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG,
4643 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG,
4663 bge_reg_put32(bgep, RDMA_CORR_CTRL_REG, regval);
4695 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG,
4826 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT);
4847 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
4852 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
5031 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0);
5032 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0);
5033 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0);
5034 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0);
5035 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0);
5036 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0);
5100 bge_reg_put32(bgep, MSI_STATUS_REG, regval);
5537 bge_reg_put32(bgep, RDMA_CORR_CTRL_REG, regval);
6389 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks);
6390 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count);
6441 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
6530 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);