Lines Matching defs:bit
41 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */
420 * Note: internally, the chip is 64-bit and BIG-endian, but
432 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte
438 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't
441 * more (under "Broadcom Mask Mode"). The bit changes the way
442 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE
445 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT
446 * bit do just what its name says -- MASK the PCI #INTA output
582 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine
748 * The DDI doesn't provide get/put functions for 128 bit data
749 * so we put RCBs out as two 64-bit chunks instead.
1059 * The DDI doesn't provide get/put functions for 128 bit data
1060 * so we put RCBs out as two 64-bit chunks instead.
1185 * bit set here -- it seems that the chip can initiate MII
1219 * Drop out early if the READ FAILED bit is set -- this chip
1229 * The PRM says to wait 5us after seeing the START bit clear
1232 * START bit is clear but the data field isn't yet valid.
1235 * except when the START bit is seen set again (see below),
1243 * we have occasionally seen the START bit set again(!) in the
1396 * see EITHER the START bit (command started but not complete)
1397 * OR the COMPLETE bit (command completed but not cleared).
1438 * clear the <complete> bit and leave the SEEPROM access
1686 * port) typically takes ~20us. So waiting a bit longer than
1723 * This code assumes that the GPIO1 bit has been wired up to the NVmem
2101 uint32_t bit;
2117 bit = APE_LOCK_GRANT_DRIVER;
2121 bit = APE_LOCK_GRANT_DRIVER;
2123 bit = 1 << bgep->pci_func;
2125 bge_ape_put32(bgep, regbase + 4 * i, bit);
2137 uint32_t bit;
2151 bit = APE_LOCK_REQ_DRIVER;
2153 bit = 1 << bgep->pci_func;
2159 bit = APE_LOCK_REQ_DRIVER;
2175 bge_ape_put32(bgep, req + off, bit);
2180 if (status == bit)
2185 if (status != bit) {
2187 bge_ape_put32(bgep, gnt + off, bit);
2198 uint32_t bit;
2212 bit = APE_LOCK_GRANT_DRIVER;
2214 bit = 1 << bgep->pci_func;
2220 bit = APE_LOCK_GRANT_DRIVER;
2231 bge_ape_put32(bgep, gnt + 4 * locknum, bit);
3119 * To reset the state machine, the <reset> bit must be written with 1;
3123 * To enable a state machine, one must set the <enable> bit, which
3126 * To disable a state machine, the <enable> bit must be cleared, but
3131 * or disable operation, returning B_TRUE on success (bit reached the
3162 * machines) have a <reset> bit (fortunately, in the same place in
3163 * each such register :-). To reset the state machine, this bit must
3167 * This code sets the bit, then polls for it to read back as zero.
3168 * The return value is B_TRUE on success (reset bit cleared itself),
3200 * resetting PCIE block and bringing PCIE link down, bit 29
3202 * while the reset bit is written.
3271 * (re)Disable interrupts as the bit can be reset after a
3321 * machines) have an <enable> bit (fortunately, in the same place in
3322 * each such register :-). To stop the state machine, this bit must
3326 * The return value is B_TRUE on success (enable bit cleared), or
3354 * have an <enable> bit, but instead we
3388 * machines) have an <enable> bit (fortunately, in the same place in
3389 * each such register :-). To start the state machine, this bit must
3393 * The return value is B_TRUE on success (enable bit set), or
3418 * have an <enable> bit, but instead we
3637 * Set or clear the PROMISCUOUS mode bit
3785 * do a fair bit of tidying first
3842 * Note: the magic number is only a 32-bit quantity, but the NIC
3843 * memory is 64-bit (and big-endian) internally. Addressing the
3844 * GENCOMM word as "the upper half of a 64-bit quantity" makes
4044 * a bit set to avoid a fifo overflow/underflow bug.
4220 * register-image (64-bit) and byte-array forms. All-zero and
4397 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit
4878 * MSI bits:The least significant MSI 16-bit word.
5009 * reasons for the ERROR bit to be asserted
5073 * bit is *zero* when the interrupt is asserted.