Lines Matching defs:bfe
51 #include "bfe.h"
68 * Each descriptor entry is bfe_desc_t structure in bfe. During TX/RX
98 * notified by an interrupt to bfe driver.
128 #define MODULE_NAME "bfe"
144 static char bfe_ident[] = "bfe driver for Broadcom BCM4401 chipsets";
147 * Function Prototypes for bfe driver.
244 #define ASSERT_ALL_LOCKS(bfe) { \
245 ASSERT(mutex_owned(&bfe->bfe_tx_ring.r_lock)); \
246 ASSERT(rw_write_held(&bfe->bfe_rwlock)); \
266 cmn_err(CE_WARN, "bfe: %s", buf);
274 bfe_grab_locks(bfe_t *bfe)
276 bfe_ring_t *tx = &bfe->bfe_tx_ring;
283 rw_enter(&bfe->bfe_rwlock, RW_WRITER);
295 bfe_release_locks(bfe_t *bfe)
297 bfe_ring_t *tx = &bfe->bfe_tx_ring;
303 rw_exit(&bfe->bfe_rwlock);
311 bfe_wait_bit(bfe_t *bfe, uint32_t reg, uint32_t bit,
318 v = INL(bfe, reg);
340 bfe_read_phy(bfe_t *bfe, uint32_t reg)
342 OUTL(bfe, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
343 OUTL(bfe, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
345 (bfe->bfe_phy_addr << BFE_MDIO_PMD_SHIFT) |
349 (void) bfe_wait_bit(bfe, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 10, 0);
351 return ((INL(bfe, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA));
355 bfe_write_phy(bfe_t *bfe, uint32_t reg, uint32_t val)
357 OUTL(bfe, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
358 OUTL(bfe, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
360 (bfe->bfe_phy_addr << BFE_MDIO_PMD_SHIFT) |
365 (void) bfe_wait_bit(bfe, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 10, 0);
372 bfe_reset_phy(bfe_t *bfe)
376 bfe_write_phy(bfe, MII_CONTROL, MII_CONTROL_RESET);
379 if (bfe_read_phy(bfe, MII_CONTROL) &
389 bfe_error(bfe->bfe_dip, "Timeout waiting for PHY to reset");
390 bfe->bfe_phy_state = BFE_PHY_RESET_TIMEOUT;
394 bfe->bfe_phy_state = BFE_PHY_RESET_DONE;
404 bfe_stop_timer(bfe_t *bfe)
406 if (bfe->bfe_periodic_id) {
407 ddi_periodic_delete(bfe->bfe_periodic_id);
408 bfe->bfe_periodic_id = NULL;
416 bfe_stop_phy(bfe_t *bfe)
418 bfe_write_phy(bfe, MII_CONTROL, MII_CONTROL_PWRDN |
421 bfe->bfe_chip.link = LINK_STATE_UNKNOWN;
422 bfe->bfe_chip.speed = 0;
423 bfe->bfe_chip.duplex = LINK_DUPLEX_UNKNOWN;
425 bfe->bfe_phy_state = BFE_PHY_STOPPED;
430 if (bfe->bfe_machdl != NULL)
431 (void) bfe_report_link(bfe);
435 bfe_probe_phy(bfe_t *bfe)
440 if (bfe->bfe_phy_addr) {
441 status = bfe_read_phy(bfe, MII_STATUS);
443 bfe_write_phy(bfe, MII_CONTROL, 0);
449 bfe->bfe_phy_addr = phy;
450 status = bfe_read_phy(bfe, MII_STATUS);
452 bfe_write_phy(bfe, MII_CONTROL, 0);
467 bfe_t *bfe = (bfe_t *)arg;
471 * We don't grab any lock because bfe can't go away.
474 if (bfe->bfe_chip_action & BFE_ACTION_RESTART) {
478 bfe_grab_locks(bfe);
479 bfe_chip_restart(bfe);
480 bfe->bfe_chip_action &= ~BFE_ACTION_RESTART;
481 bfe->bfe_chip_action &= ~BFE_ACTION_RESTART_FAULT;
482 bfe->bfe_chip_action &= ~BFE_ACTION_RESTART_PKT;
483 bfe_release_locks(bfe);
484 mac_tx_update(bfe->bfe_machdl);
489 rw_enter(&bfe->bfe_rwlock, RW_READER);
491 if (bfe->bfe_chip_state == BFE_CHIP_ACTIVE) {
495 if (bfe->bfe_tx_stall_time != 0 &&
496 hr > bfe->bfe_tx_stall_time) {
497 DTRACE_PROBE2(chip__restart, int, bfe->bfe_unit,
499 bfe->bfe_chip_action |=
501 bfe->bfe_tx_stall_time = 0;
505 if (bfe->bfe_phy_state == BFE_PHY_STARTED) {
509 if (bfe_check_link(bfe)) {
510 bfe_report_link(bfe);
511 if (bfe->bfe_chip.link == LINK_STATE_UP) {
514 val = INL(bfe, BFE_TX_CTRL);
516 if (bfe->bfe_chip.duplex == LINK_DUPLEX_FULL) {
518 flow = INL(bfe, BFE_RXCONF);
520 OUTL(bfe, BFE_RXCONF, flow);
522 flow = INL(bfe, BFE_MAC_FLOW);
524 OUTL(bfe, BFE_MAC_FLOW, flow);
529 OUTL(bfe, BFE_TX_CTRL, val);
531 int, bfe->bfe_unit);
536 rw_exit(&bfe->bfe_rwlock);
539 mac_tx_update(bfe->bfe_machdl);
546 bfe_startup_phy(bfe_t *bfe)
552 if (bfe_probe_phy(bfe) == BFE_FAILURE) {
553 bfe->bfe_phy_state = BFE_PHY_NOTFOUND;
557 (void) bfe_reset_phy(bfe);
559 phyid1 = bfe_read_phy(bfe, MII_PHYIDH);
560 phyid2 = bfe_read_phy(bfe, MII_PHYIDL);
561 bfe->bfe_phy_id = (phyid1 << 16) | phyid2;
563 bmsr = bfe_read_phy(bfe, MII_STATUS);
564 anar = bfe_read_phy(bfe, MII_AN_ADVERT);
574 bfe->bfe_chip.bmsr = bmsr;
579 bfe->bfe_cap_aneg = bfe->bfe_cap_100T4 =
580 bfe->bfe_cap_100fdx = bfe->bfe_cap_100hdx =
581 bfe->bfe_cap_10fdx = bfe->bfe_cap_10hdx = 0;
587 if (!(bfe->bfe_chip_action & BFE_ACTION_RESTART_SETPROP)) {
598 bfe->bfe_cap_100fdx = 1;
601 bfe->bfe_adv_100fdx = 1;
603 } else if (bfe->bfe_adv_100fdx) {
610 bfe->bfe_cap_100T4 = 1;
613 bfe->bfe_adv_100T4 = 1;
615 } else if (bfe->bfe_adv_100T4) {
622 bfe->bfe_cap_100hdx = 1;
625 bfe->bfe_adv_100hdx = 1;
627 } else if (bfe->bfe_adv_100hdx) {
634 bfe->bfe_cap_10fdx = 1;
637 bfe->bfe_adv_10fdx = 1;
639 } else if (bfe->bfe_adv_10fdx) {
646 bfe->bfe_cap_10hdx = 1;
649 bfe->bfe_adv_10hdx = 1;
651 } else if (bfe->bfe_adv_10hdx) {
658 bfe->bfe_cap_aneg = 1;
660 bfe->bfe_adv_aneg = 1;
666 bfe_error(bfe->bfe_dip,
668 bfe_stop_phy(bfe);
669 bfe_report_link(bfe);
677 bfe->bfe_chip_action &= ~BFE_ACTION_RESTART_SETPROP;
681 if (bfe->bfe_adv_aneg && (bmsr & MII_STATUS_CANAUTONEG)) {
684 if (bfe->bfe_adv_100fdx)
686 else if (bfe->bfe_adv_100hdx)
688 else if (bfe->bfe_adv_10fdx)
695 bfe_write_phy(bfe, MII_AN_ADVERT, anar);
698 bfe_write_phy(bfe, MII_CONTROL, bmcr);
700 bfe->bfe_mii_anar = anar;
701 bfe->bfe_mii_bmcr = bmcr;
702 bfe->bfe_phy_state = BFE_PHY_STARTED;
704 if (bfe->bfe_periodic_id == NULL) {
705 bfe->bfe_periodic_id = ddi_periodic_add(bfe_timeout,
706 (void *)bfe, BFE_TIMEOUT_INTERVAL, DDI_IPL_0);
708 DTRACE_PROBE1(first__timeout, int, bfe->bfe_unit);
711 DTRACE_PROBE4(phy_started, int, bfe->bfe_unit,
721 bfe_report_link(bfe_t *bfe)
723 mac_link_update(bfe->bfe_machdl, bfe->bfe_chip.link);
730 bfe_check_link(bfe_t *bfe)
735 speed = bfe->bfe_chip.speed;
736 duplex = bfe->bfe_chip.duplex;
737 link = bfe->bfe_chip.link;
739 bmsr = bfe_read_phy(bfe, MII_STATUS);
740 bfe->bfe_mii_bmsr = bmsr;
742 bmcr = bfe_read_phy(bfe, MII_CONTROL);
744 anar = bfe_read_phy(bfe, MII_AN_ADVERT);
745 bfe->bfe_mii_anar = anar;
747 anlpar = bfe_read_phy(bfe, MII_AN_LPABLE);
748 bfe->bfe_mii_anlpar = anlpar;
750 bfe->bfe_mii_exp = bfe_read_phy(bfe, MII_AN_EXPANSION);
755 if (bfe->bfe_mii_exp == 0xffff) {
756 bfe->bfe_mii_exp = 0;
760 bfe->bfe_chip.link = LINK_STATE_DOWN;
761 bfe->bfe_chip.speed = 0;
762 bfe->bfe_chip.duplex = LINK_DUPLEX_UNKNOWN;
766 bfe->bfe_chip.link = LINK_STATE_UP;
771 bfe->bfe_chip.speed = 100000000;
773 bfe->bfe_chip.speed = 10000000;
776 bfe->bfe_chip.duplex = LINK_DUPLEX_FULL;
778 bfe->bfe_chip.duplex = LINK_DUPLEX_HALF;
782 bfe->bfe_chip.speed = 0;
783 bfe->bfe_chip.duplex = LINK_DUPLEX_UNKNOWN;
785 bfe->bfe_chip.speed = 100000000;
786 bfe->bfe_chip.duplex = LINK_DUPLEX_FULL;
788 bfe->bfe_chip.speed = 100000000;
789 bfe->bfe_chip.duplex = LINK_DUPLEX_HALF;
791 bfe->bfe_chip.speed = 100000000;
792 bfe->bfe_chip.duplex = LINK_DUPLEX_HALF;
794 bfe->bfe_chip.speed = 10000000;
795 bfe->bfe_chip.duplex = LINK_DUPLEX_FULL;
797 bfe->bfe_chip.speed = 10000000;
798 bfe->bfe_chip.duplex = LINK_DUPLEX_HALF;
800 bfe->bfe_chip.speed = 0;
801 bfe->bfe_chip.duplex = LINK_DUPLEX_UNKNOWN;
809 if (speed != bfe->bfe_chip.speed ||
810 duplex != bfe->bfe_chip.duplex ||
811 link != bfe->bfe_chip.link) {
819 bfe_cam_write(bfe_t *bfe, uchar_t *d, int index)
828 OUTL(bfe, BFE_CAM_DATA_LO, v);
833 OUTL(bfe, BFE_CAM_DATA_HI, v);
834 OUTL(bfe, BFE_CAM_CTRL, (BFE_CAM_WRITE |
836 (void) bfe_wait_bit(bfe, BFE_CAM_CTRL, BFE_CAM_BUSY, 10, 1);
843 bfe_chip_halt(bfe_t *bfe)
848 OUTL(bfe, BFE_INTR_MASK, 0);
849 FLUSH(bfe, BFE_INTR_MASK);
851 OUTL(bfe, BFE_ENET_CTRL, BFE_ENET_DISABLE);
856 (void) bfe_wait_bit(bfe, BFE_ENET_CTRL, BFE_ENET_DISABLE, 20, 1);
861 OUTL(bfe, BFE_DMARX_CTRL, 0);
862 OUTL(bfe, BFE_DMATX_CTRL, 0);
866 bfe->bfe_chip_state = BFE_CHIP_HALT;
870 bfe_chip_restart(bfe_t *bfe)
872 DTRACE_PROBE2(chip__restart, int, bfe->bfe_unit,
873 int, bfe->bfe_chip_action);
878 bfe_chip_halt(bfe);
879 bfe_stop_phy(bfe);
880 bfe->bfe_chip_state = BFE_CHIP_STOPPED;
885 bfe_init_vars(bfe);
890 bfe_chip_reset(bfe);
895 bfe_tx_desc_init(&bfe->bfe_tx_ring);
896 bfe_rx_desc_init(&bfe->bfe_rx_ring);
898 bfe->bfe_chip_state = BFE_CHIP_ACTIVE;
899 bfe_set_rx_mode(bfe);
900 bfe_enable_chip_intrs(bfe);
907 bfe_core_disable(bfe_t *bfe)
909 if ((INL(bfe, BFE_SBTMSLOW) & BFE_RESET))
912 OUTL(bfe, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
913 (void) bfe_wait_bit(bfe, BFE_SBTMSLOW, BFE_REJECT, 100, 0);
914 (void) bfe_wait_bit(bfe, BFE_SBTMSHIGH, BFE_BUSY, 100, 1);
915 OUTL(bfe, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | BFE_RESET));
916 FLUSH(bfe, BFE_SBTMSLOW);
918 OUTL(bfe, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
926 bfe_core_reset(bfe_t *bfe)
933 bfe_core_disable(bfe);
935 OUTL(bfe, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
936 FLUSH(bfe, BFE_SBTMSLOW);
939 if (INL(bfe, BFE_SBTMSHIGH) & BFE_SERR)
940 OUTL(bfe, BFE_SBTMSHIGH, 0);
942 val = INL(bfe, BFE_SBIMSTATE);
944 OUTL(bfe, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
946 OUTL(bfe, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
947 FLUSH(bfe, BFE_SBTMSLOW);
950 OUTL(bfe, BFE_SBTMSLOW, BFE_CLOCK);
951 FLUSH(bfe, BFE_SBTMSLOW);
956 bfe_setup_config(bfe_t *bfe, uint32_t cores)
963 bar_orig = pci_config_get32(bfe->bfe_conf_handle, BFE_BAR0_WIN);
964 pci_config_put32(bfe->bfe_conf_handle, BFE_BAR0_WIN, BFE_REG_PCI);
967 val = INL(bfe, BFE_SBIDHIGH) & BFE_IDH_CORE;
969 val = INL(bfe, BFE_SBINTVEC);
971 OUTL(bfe, BFE_SBINTVEC, val);
973 val = INL(bfe, BFE_SSB_PCI_TRANS_2);
975 OUTL(bfe, BFE_SSB_PCI_TRANS_2, val);
980 pci_config_put32(bfe->bfe_conf_handle, BFE_BAR0_WIN, bar_orig);
987 bfe_chip_reset(bfe_t *bfe)
992 bfe_setup_config(bfe, BFE_INTVEC_ENET0);
995 val = INL(bfe, BFE_SBTMSLOW) &
999 OUTL(bfe, BFE_RCV_LAZY, 0);
1000 OUTL(bfe, BFE_ENET_CTRL, BFE_ENET_DISABLE);
1001 (void) bfe_wait_bit(bfe, BFE_ENET_CTRL,
1003 OUTL(bfe, BFE_DMATX_CTRL, 0);
1004 FLUSH(bfe, BFE_DMARX_STAT);
1006 if (INL(bfe, BFE_DMARX_STAT) & BFE_STAT_EMASK) {
1007 (void) bfe_wait_bit(bfe, BFE_DMARX_STAT, BFE_STAT_SIDLE,
1010 OUTL(bfe, BFE_DMARX_CTRL, 0);
1013 bfe_core_reset(bfe);
1014 bfe_clear_stats(bfe);
1016 OUTL(bfe, BFE_MDIO_CTRL, 0x8d);
1017 val = INL(bfe, BFE_DEVCTRL);
1019 OUTL(bfe, BFE_ENET_CTRL, BFE_ENET_EPSEL);
1020 else if (INL(bfe, BFE_DEVCTRL & BFE_EPR)) {
1021 OUTL_AND(bfe, BFE_DEVCTRL, ~BFE_EPR);
1025 OUTL_OR(bfe, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
1027 OUTL_AND(bfe, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
1029 OUTL(bfe, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
1032 OUTL_OR(bfe, BFE_RCV_LAZY, 0);
1034 OUTL(bfe, BFE_RXMAXLEN, bfe->bfe_rx_ring.r_buf_len);
1035 OUTL(bfe, BFE_TXMAXLEN, bfe->bfe_tx_ring.r_buf_len);
1037 OUTL(bfe, BFE_TX_WMARK, 56);
1040 OUTL(bfe, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
1045 OUTL(bfe, BFE_DMATX_ADDR,
1046 bfe->bfe_tx_ring.r_desc_cookie.dmac_laddress + BFE_PCI_DMA);
1048 OUTL(bfe, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT)
1051 OUTL(bfe, BFE_DMARX_ADDR,
1052 bfe->bfe_rx_ring.r_desc_cookie.dmac_laddress + BFE_PCI_DMA);
1054 (void) bfe_startup_phy(bfe);
1056 bfe->bfe_chip_state = BFE_CHIP_INITIALIZED;
1063 bfe_enable_chip_intrs(bfe_t *bfe)
1066 OUTL(bfe, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1069 OUTL(bfe, BFE_INTR_MASK, BFE_IMASK_DEF);
1076 bfe_set_rx_mode(bfe_t *bfe)
1086 if (bfe->bfe_chip_state == BFE_CHIP_SUSPENDED)
1089 val = INL(bfe, BFE_RXCONF);
1094 if ((bfe->bfe_chip_mode & BFE_RX_MODE_ENABLE) == 0) {
1095 OUTL(bfe, BFE_CAM_CTRL, 0);
1096 FLUSH(bfe, BFE_CAM_CTRL);
1097 } else if (bfe->bfe_chip_mode & BFE_RX_MODE_PROMISC) {
1101 if (bfe->bfe_chip_state == BFE_CHIP_ACTIVE) {
1103 OUTL(bfe, BFE_RXCONF, val |
1105 FLUSH(bfe, BFE_RXCONF);
1109 OUTL(bfe, BFE_CAM_CTRL, 0);
1110 FLUSH(bfe, BFE_CAM_CTRL);
1118 bfe_cam_write(bfe, (uchar_t *)mac, i);
1121 bfe_cam_write(bfe, bfe->bfe_ether_addr, i);
1124 OUTL_OR(bfe, BFE_CAM_CTRL, BFE_CAM_ENABLE);
1125 FLUSH(bfe, BFE_CAM_CTRL);
1128 DTRACE_PROBE2(rx__mode__filter, int, bfe->bfe_unit,
1131 OUTL(bfe, BFE_RXCONF, val);
1132 FLUSH(bfe, BFE_RXCONF);
1139 bfe_init_vars(bfe_t *bfe)
1141 bfe->bfe_chip_mode = BFE_RX_MODE_ENABLE;
1144 bfe->bfe_chip.link = LINK_STATE_UNKNOWN;
1145 bfe->bfe_chip.speed = 0;
1146 bfe->bfe_chip.duplex = LINK_DUPLEX_UNKNOWN;
1148 bfe->bfe_periodic_id = NULL;
1149 bfe->bfe_chip_state = BFE_CHIP_UNINITIALIZED;
1151 bfe->bfe_tx_stall_time = 0;
1224 bfe_chip_start(bfe_t *bfe)
1226 ASSERT_ALL_LOCKS(bfe);
1231 bfe_chip_halt(bfe);
1232 bfe_stop_phy(bfe);
1237 bfe_chip_reset(bfe);
1242 bfe_tx_desc_init(&bfe->bfe_tx_ring);
1243 bfe_rx_desc_init(&bfe->bfe_rx_ring);
1245 bfe->bfe_chip_state = BFE_CHIP_ACTIVE;
1246 bfe->bfe_chip_mode |= BFE_RX_MODE_ENABLE;
1247 bfe_set_rx_mode(bfe);
1248 bfe_enable_chip_intrs(bfe);
1251 (void) bfe_check_link(bfe);
1261 bfe_clear_stats(bfe_t *bfe)
1265 OUTL(bfe, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
1271 (void) INL(bfe, r);
1274 (void) INL(bfe, r);
1281 bfe_gather_stats(bfe_t *bfe)
1287 v = &bfe->bfe_hw_stats.tx_good_octets;
1289 *v += INL(bfe, r);
1293 v = &bfe->bfe_hw_stats.rx_good_octets;
1295 *v += INL(bfe, r);
1323 bfe->bfe_stats.ether_stat_carrier_errors =
1324 bfe->bfe_hw_stats.tx_carrier_lost;
1326 /* txerr += bfe->bfe_hw_stats.tx_carrier_lost; */
1328 bfe->bfe_stats.ether_stat_ex_collisions =
1329 bfe->bfe_hw_stats.tx_excessive_cols;
1330 txerr += bfe->bfe_hw_stats.tx_excessive_cols;
1331 coll += bfe->bfe_hw_stats.tx_excessive_cols;
1333 bfe->bfe_stats.ether_stat_fcs_errors =
1334 bfe->bfe_hw_stats.rx_crc_errs;
1335 rxerr += bfe->bfe_hw_stats.rx_crc_errs;
1337 bfe->bfe_stats.ether_stat_first_collisions =
1338 bfe->bfe_hw_stats.tx_single_cols;
1339 coll += bfe->bfe_hw_stats.tx_single_cols;
1340 bfe->bfe_stats.ether_stat_multi_collisions =
1341 bfe->bfe_hw_stats.tx_multiple_cols;
1342 coll += bfe->bfe_hw_stats.tx_multiple_cols;
1344 bfe->bfe_stats.ether_stat_toolong_errors =
1345 bfe->bfe_hw_stats.rx_oversize_pkts;
1346 rxerr += bfe->bfe_hw_stats.rx_oversize_pkts;
1348 bfe->bfe_stats.ether_stat_tooshort_errors =
1349 bfe->bfe_hw_stats.rx_undersize;
1350 rxerr += bfe->bfe_hw_stats.rx_undersize;
1352 bfe->bfe_stats.ether_stat_tx_late_collisions +=
1353 bfe->bfe_hw_stats.tx_late_cols;
1355 bfe->bfe_stats.ether_stat_defer_xmts +=
1356 bfe->bfe_hw_stats.tx_defered;
1358 bfe->bfe_stats.ether_stat_macrcv_errors += rxerr;
1359 bfe->bfe_stats.ether_stat_macxmt_errors += txerr;
1361 bfe->bfe_stats.collisions += coll;
1370 bfe_t *bfe = (bfe_t *)arg;
1374 rw_enter(&bfe->bfe_rwlock, RW_READER);
1387 if (bfe->bfe_chip_state == BFE_CHIP_ACTIVE) {
1391 bfe_gather_stats(bfe);
1393 v = bfe->bfe_chip.speed;
1397 v = bfe->bfe_adv_100T4;
1401 v = (bfe->bfe_mii_anar & MII_ABILITY_100BASE_TX_FD) != 0;
1405 v = (bfe->bfe_mii_anar & MII_ABILITY_100BASE_TX) != 0;
1409 v = (bfe->bfe_mii_anar & MII_ABILITY_10BASE_T_FD) != 0;
1413 v = (bfe->bfe_mii_anar & MII_ABILITY_10BASE_T) != 0;
1421 v = bfe->bfe_adv_aneg;
1425 v = (bfe->bfe_mii_anar & MII_ABILITY_PAUSE) != 0;
1429 v = (bfe->bfe_mii_anar & MII_AN_ADVERT_REMFAULT) != 0;
1434 v = bfe->bfe_stats.ether_stat_align_errors;
1438 v = (bfe->bfe_mii_bmsr & MII_STATUS_100_BASE_T4) != 0;
1442 v = (bfe->bfe_mii_bmsr & MII_STATUS_100_BASEX_FD) != 0;
1446 v = (bfe->bfe_mii_bmsr & MII_STATUS_100_BASEX) != 0;
1450 v = (bfe->bfe_mii_bmsr & MII_STATUS_10_FD) != 0;
1454 v = (bfe->bfe_mii_bmsr & MII_STATUS_10) != 0;
1462 v = ((bfe->bfe_mii_bmsr & MII_STATUS_CANAUTONEG) != 0);
1470 v = (bfe->bfe_mii_bmsr & MII_STATUS_REMFAULT) != 0;
1474 v = bfe->bfe_stats.ether_stat_carrier_errors;
1482 v = bfe->bfe_stats.ether_stat_defer_xmts;
1487 v = bfe->bfe_stats.ether_stat_ex_collisions;
1492 v = bfe->bfe_stats.ether_stat_fcs_errors;
1497 v = bfe->bfe_stats.ether_stat_first_collisions;
1505 v = (bfe->bfe_mii_bmcr & MII_CONTROL_ANE) != 0 &&
1506 (bfe->bfe_mii_bmsr & MII_STATUS_ANDONE) != 0;
1510 v = bfe->bfe_chip.duplex;
1514 v = (bfe->bfe_mii_anlpar & MII_ABILITY_100BASE_T4) != 0;
1518 v = (bfe->bfe_mii_anlpar & MII_ABILITY_100BASE_TX_FD) != 0;
1522 v = (bfe->bfe_mii_anlpar & MII_ABILITY_100BASE_TX) != 0;
1526 v = (bfe->bfe_mii_anlpar & MII_ABILITY_10BASE_T_FD) != 0;
1530 v = (bfe->bfe_mii_anlpar & MII_ABILITY_10BASE_T) != 0;
1538 v = (bfe->bfe_mii_exp & MII_AN_EXP_LPCANAN) != 0;
1542 v = (bfe->bfe_mii_anlpar & MII_ABILITY_PAUSE) != 0;
1546 v = (bfe->bfe_mii_anlpar & MII_STATUS_REMFAULT) != 0;
1550 v = bfe->bfe_stats.ether_stat_macrcv_errors;
1554 v = bfe->bfe_stats.ether_stat_macxmt_errors;
1558 v = bfe->bfe_stats.ether_stat_multi_collisions;
1566 v = bfe->bfe_stats.ether_stat_toolong_errors;
1570 v = bfe->bfe_stats.ether_stat_tooshort_errors;
1574 v = bfe->bfe_stats.ether_stat_tx_late_collisions;
1578 v = bfe->bfe_phy_addr;
1582 v = bfe->bfe_phy_id;
1586 v = bfe->bfe_stats.brdcstrcv;
1590 v = bfe->bfe_stats.brdcstxmt;
1594 v = bfe->bfe_stats.multixmt;
1598 v = bfe->bfe_stats.collisions;
1602 v = bfe->bfe_stats.ierrors;
1606 v = bfe->bfe_stats.ipackets;
1610 v = bfe->bfe_stats.multircv;
1614 v = bfe->bfe_stats.norcvbuf;
1618 v = bfe->bfe_stats.noxmtbuf;
1622 v = bfe->bfe_stats.obytes;
1627 v = bfe->bfe_stats.ether_stat_macxmt_errors;
1631 v = bfe->bfe_stats.opackets;
1635 v = bfe->bfe_stats.rbytes;
1639 v = bfe->bfe_stats.underflows;
1643 v = bfe->bfe_stats.overflows;
1647 rw_exit(&bfe->bfe_rwlock);
1657 bfe_t *bfe = (bfe_t *)arg;
1663 bcopy(&bfe->bfe_chip.duplex, val, sizeof (link_duplex_t));
1668 bcopy(&bfe->bfe_chip.speed, val, sizeof (uint64_t));
1672 *(uint8_t *)val = bfe->bfe_adv_aneg;
1676 *(uint8_t *)val = bfe->bfe_adv_100fdx;
1680 *(uint8_t *)val = bfe->bfe_adv_100fdx;
1684 *(uint8_t *)val = bfe->bfe_adv_100hdx;
1688 *(uint8_t *)val = bfe->bfe_adv_100hdx;
1692 *(uint8_t *)val = bfe->bfe_adv_10fdx;
1696 *(uint8_t *)val = bfe->bfe_adv_10fdx;
1700 *(uint8_t *)val = bfe->bfe_adv_10hdx;
1704 *(uint8_t *)val = bfe->bfe_adv_10hdx;
1708 *(uint8_t *)val = bfe->bfe_adv_100T4;
1712 *(uint8_t *)val = bfe->bfe_adv_100T4;
1727 bfe_t *bfe = (bfe_t *)arg;
1742 mac_prop_info_set_default_uint8(prh, bfe->bfe_cap_aneg);
1746 mac_prop_info_set_default_uint8(prh, bfe->bfe_cap_100fdx);
1750 mac_prop_info_set_default_uint8(prh, bfe->bfe_cap_100hdx);
1754 mac_prop_info_set_default_uint8(prh, bfe->bfe_cap_10fdx);
1758 mac_prop_info_set_default_uint8(prh, bfe->bfe_cap_10hdx);
1769 bfe_t *bfe = (bfe_t *)arg;
1776 advp = &bfe->bfe_adv_100fdx;
1777 capp = &bfe->bfe_cap_100fdx;
1781 advp = &bfe->bfe_adv_100hdx;
1782 capp = &bfe->bfe_cap_100hdx;
1786 advp = &bfe->bfe_adv_10fdx;
1787 capp = &bfe->bfe_cap_10fdx;
1791 advp = &bfe->bfe_adv_10hdx;
1792 capp = &bfe->bfe_cap_10hdx;
1796 advp = &bfe->bfe_adv_aneg;
1797 capp = &bfe->bfe_cap_aneg;
1807 bfe_grab_locks(bfe);
1812 bfe->bfe_chip_action = BFE_ACTION_RESTART_SETPROP;
1813 if (bfe->bfe_chip_state == BFE_CHIP_ACTIVE) {
1818 bfe_stop_timer(bfe);
1820 bfe->bfe_chip_action |= BFE_ACTION_RESTART;
1822 bfe_chip_restart(bfe);
1828 bfe->bfe_chip_action &= ~(BFE_ACTION_RESTART);
1833 bfe_release_locks(bfe);
1837 mac_tx_update(bfe->bfe_machdl);
1846 bfe_t *bfe = (bfe_t *)arg;
1848 bfe_grab_locks(bfe);
1849 bcopy(ea, bfe->bfe_ether_addr, ETHERADDRL);
1850 bfe_set_rx_mode(bfe);
1851 bfe_release_locks(bfe);
1858 bfe_t *bfe = (bfe_t *)arg;
1860 bfe_grab_locks(bfe);
1861 if (bfe_chip_start(bfe) == DDI_FAILURE) {
1862 bfe_release_locks(bfe);
1866 bfe_release_locks(bfe);
1868 mac_tx_update(bfe->bfe_machdl);
1876 bfe_t *bfe = (bfe_t *)arg;
1882 bfe_stop_timer(bfe);
1884 bfe_grab_locks(bfe);
1889 bfe_chip_halt(bfe);
1890 bfe_stop_phy(bfe);
1892 bfe->bfe_chip_state = BFE_CHIP_STOPPED;
1897 bfe_chip_reset(bfe);
1902 bfe->bfe_chip_mode &= ~BFE_RX_MODE_ENABLE;
1903 bfe_set_rx_mode(bfe);
1905 bfe_release_locks(bfe);
1912 bfe_send_a_packet(bfe_t *bfe, mblk_t *mp)
1914 bfe_ring_t *r = &bfe->bfe_tx_ring;
1938 bfe->bfe_stats.noxmtbuf++;
1939 bfe->bfe_tx_resched = 1;
1955 bfe->bfe_stats.multixmt++;
1957 bfe->bfe_stats.brdcstxmt++;
1959 bfe->bfe_stats.opackets++;
1960 bfe->bfe_stats.obytes += pktlen;
1997 OUTL(bfe, BFE_DMATX_PTR, next * sizeof (bfe_desc_t));
1998 FLUSH(bfe, BFE_DMATX_PTR);
2006 bfe->bfe_tx_stall_time = gethrtime() + (5 * 1000000000ULL);
2014 bfe_t *bfe = (bfe_t *)arg;
2015 bfe_ring_t *r = &bfe->bfe_tx_ring;
2020 if (bfe->bfe_chip_state != BFE_CHIP_ACTIVE) {
2021 DTRACE_PROBE1(tx__chip__not__active, int, bfe->bfe_unit);
2033 if (bfe_send_a_packet(bfe, mp) == BFE_FAILURE) {
2048 bfe_t *bfe = (bfe_t *)arg;
2050 bfe_grab_locks(bfe);
2051 if (bfe->bfe_chip_state != BFE_CHIP_ACTIVE) {
2052 bfe_release_locks(bfe);
2058 bfe->bfe_chip_mode |= BFE_RX_MODE_PROMISC;
2060 bfe->bfe_chip_mode &= ~BFE_RX_MODE_PROMISC;
2063 bfe_set_rx_mode(bfe);
2064 bfe_release_locks(bfe);
2099 bfe_error_handler(bfe_t *bfe, int intr_mask)
2104 bfe->bfe_stats.overflows++;
2105 bfe->bfe_chip_action |=
2111 bfe->bfe_stats.underflows++;
2117 bfe_error(bfe->bfe_dip,
2119 bfe->bfe_chip_action |=
2126 bfe_error(bfe->bfe_dip, "Descriptor Error. Restarting Chip");
2132 bfe_error(bfe->bfe_dip,
2134 bfe->bfe_stats.ether_stat_macrcv_errors++;
2135 bfe->bfe_chip_action |=
2140 v = INL(bfe, BFE_DMATX_STAT);
2144 bfe->bfe_stats.ether_stat_macxmt_errors++;
2145 bfe_error(bfe->bfe_dip,
2150 v = INL(bfe, BFE_DMARX_STAT);
2152 bfe->bfe_stats.ierrors++;
2153 bfe_error(bfe->bfe_dip,
2158 bfe->bfe_chip_action |=
2162 bfe_chip_halt(bfe);
2169 bfe_rx_desc_buf_reinit(bfe_t *bfe, uint_t slot)
2171 bfe_ring_t *r = &bfe->bfe_rx_ring;
2197 bfe_receive(bfe_t *bfe, int intr_mask)
2204 bfe_ring_t *r = &bfe->bfe_rx_ring;
2207 rxstat = INL(bfe, BFE_DMARX_STAT);
2213 DTRACE_PROBE3(receive, int, bfe->bfe_unit,
2247 bfe_rx_desc_buf_reinit(bfe, i);
2269 bfe->bfe_stats.ipackets++;
2272 bfe->bfe_stats.rbytes += len;
2275 bfe->bfe_stats.brdcstrcv++;
2277 bfe->bfe_stats.multircv++;
2279 bfe->bfe_stats.norcvbuf++;
2281 bfe_rx_desc_buf_reinit(bfe, i);
2289 bfe_rx_desc_buf_reinit(bfe, i);
2345 bfe_tx_done(bfe_t *bfe, int intr_mask)
2347 bfe_ring_t *r = &bfe->bfe_tx_ring;
2353 if (bfe->bfe_tx_resched) {
2355 bfe->bfe_tx_resched = 0;
2368 bfe_t *bfe = (void *)arg1;
2377 rw_enter(&bfe->bfe_rwlock, RW_READER);
2383 intr_stat = INL(bfe, BFE_INTR_STAT);
2385 OUTL(bfe, BFE_INTR_STAT, intr_stat);
2386 (void) INL(bfe, BFE_INTR_STAT);
2389 rw_exit(&bfe->bfe_rwlock);
2393 DTRACE_PROBE2(bfe__interrupt, int, bfe->bfe_unit,
2396 if (bfe->bfe_chip_state != BFE_CHIP_ACTIVE) {
2400 if (bfe->bfe_chip_state == BFE_CHIP_SUSPENDED) {
2401 rw_exit(&bfe->bfe_rwlock);
2403 bfe->bfe_unit);
2410 bfe_chip_halt(bfe);
2411 rw_exit(&bfe->bfe_rwlock);
2413 bfe->bfe_unit);
2419 rx_head = bfe_receive(bfe, intr_stat);
2424 resched = bfe_tx_done(bfe, intr_stat);
2429 bfe_error_handler(bfe, intr_stat);
2432 rw_exit(&bfe->bfe_rwlock);
2438 mac_rx(bfe->bfe_machdl, 0, rx_head);
2445 mac_tx_update(bfe->bfe_machdl);
2454 bfe_remove_intr(bfe_t *bfe)
2456 (void) ddi_intr_remove_handler(bfe->bfe_intrhdl);
2457 (void) ddi_intr_free(bfe->bfe_intrhdl);
2464 bfe_add_intr(bfe_t *bfe)
2469 ret = ddi_intr_alloc(bfe->bfe_dip, &bfe->bfe_intrhdl,
2477 bfe_error(bfe->bfe_dip, "ddi_intr_alloc() failed"
2482 ret = ddi_intr_add_handler(bfe->bfe_intrhdl, bfe_interrupt, bfe, NULL);
2484 bfe_error(bfe->bfe_dip, "ddi_intr_add_handler() failed");
2485 (void) ddi_intr_free(bfe->bfe_intrhdl);
2489 ret = ddi_intr_get_pri(bfe->bfe_intrhdl, &bfe->bfe_intrpri);
2491 bfe_error(bfe->bfe_dip, "ddi_intr_get_pri() failed");
2492 bfe_remove_intr(bfe);
2504 bfe_identify_hardware(bfe_t *bfe)
2509 vid = pci_config_get16(bfe->bfe_conf_handle, PCI_CONF_VENID);
2510 did = pci_config_get16(bfe->bfe_conf_handle, PCI_CONF_DEVID);
2519 bfe_error(bfe->bfe_dip, "bfe driver is attaching to unknown pci%d,%d"
2529 bfe_regs_map(bfe_t *bfe)
2531 dev_info_t *dip = bfe->bfe_dip;
2534 ret = ddi_regs_map_setup(dip, 1, &bfe->bfe_mem_regset.addr, 0, 0,
2535 &bfe_dev_attr, &bfe->bfe_mem_regset.hdl);
2538 bfe_error(bfe->bfe_dip, "ddi_regs_map_setup failed");
2546 bfe_unmap_regs(bfe_t *bfe)
2548 ddi_regs_map_free(&bfe->bfe_mem_regset.hdl);
2552 bfe_get_chip_config(bfe_t *bfe)
2561 prom[i] = INL(bfe, BFE_EEPROM_BASE + i * sizeof (uint32_t));
2564 bfe->bfe_dev_addr[0] = bfe->bfe_ether_addr[0] =
2565 INB(bfe, BFE_EEPROM_BASE + 79);
2567 bfe->bfe_dev_addr[1] = bfe->bfe_ether_addr[1] =
2568 INB(bfe, BFE_EEPROM_BASE + 78);
2570 bfe->bfe_dev_addr[2] = bfe->bfe_ether_addr[2] =
2571 INB(bfe, BFE_EEPROM_BASE + 81);
2573 bfe->bfe_dev_addr[3] = bfe->bfe_ether_addr[3] =
2574 INB(bfe, BFE_EEPROM_BASE + 80);
2576 bfe->bfe_dev_addr[4] = bfe->bfe_ether_addr[4] =
2577 INB(bfe, BFE_EEPROM_BASE + 83);
2579 bfe->bfe_dev_addr[5] = bfe->bfe_ether_addr[5] =
2580 INB(bfe, BFE_EEPROM_BASE + 82);
2582 bfe->bfe_phy_addr = -1;
2591 bfe_ring_buf_alloc(bfe_t *bfe, bfe_ring_t *r, int slot, int d)
2596 err = ddi_dma_alloc_handle(bfe->bfe_dip,
2601 bfe_error(bfe->bfe_dip, " bfe_ring_buf_alloc() :"
2613 bfe_error(bfe->bfe_dip, " bfe_ring_buf_alloc() :"
2627 bfe_error(bfe->bfe_dip, " bfe_ring_buf_alloc() :"
2633 bfe_error(bfe->bfe_dip, " bfe_ring_buf_alloc() :"
2683 bfe_ring_desc_alloc(bfe_t *bfe, bfe_ring_t *r, int d)
2691 ASSERT(bfe != NULL);
2698 err = ddi_dma_alloc_handle(bfe->bfe_dip, &bfe_dma_attr_desc,
2702 bfe_error(bfe->bfe_dip, "bfe_ring_desc_alloc() failed on"
2715 bfe_error(bfe->bfe_dip, "bfe_ring_desc_alloc() failed on"
2729 bfe_error(bfe->bfe_dip, "bfe_ring_desc_alloc() failed on"
2755 if (bfe_ring_buf_alloc(bfe, r, i, d) != DDI_SUCCESS) {
2776 bfe_rings_alloc(bfe_t *bfe)
2779 mutex_init(&bfe->bfe_tx_ring.r_lock, NULL, MUTEX_DRIVER, NULL);
2780 bfe->bfe_tx_ring.r_lockp = &bfe->bfe_tx_ring.r_lock;
2781 bfe->bfe_tx_ring.r_buf_len = BFE_MTU + sizeof (struct ether_header) +
2783 bfe->bfe_tx_ring.r_ndesc = TX_NUM_DESC;
2784 bfe->bfe_tx_ring.r_bfe = bfe;
2785 bfe->bfe_tx_ring.r_avail_desc = TX_NUM_DESC;
2788 mutex_init(&bfe->bfe_rx_ring.r_lock, NULL, MUTEX_DRIVER, NULL);
2789 bfe->bfe_rx_ring.r_lockp = &bfe->bfe_rx_ring.r_lock;
2790 bfe->bfe_rx_ring.r_buf_len = BFE_MTU + sizeof (struct ether_header) +
2792 bfe->bfe_rx_ring.r_ndesc = RX_NUM_DESC;
2793 bfe->bfe_rx_ring.r_bfe = bfe;
2794 bfe->bfe_rx_ring.r_avail_desc = RX_NUM_DESC;
2797 if (bfe_ring_desc_alloc(bfe, &bfe->bfe_tx_ring,
2802 if (bfe_ring_desc_alloc(bfe, &bfe->bfe_rx_ring,
2805 bfe_ring_desc_free(&bfe->bfe_tx_ring);
2809 bfe->bfe_tx_ring.r_flags = BFE_RING_ALLOCATED;
2810 bfe->bfe_rx_ring.r_flags = BFE_RING_ALLOCATED;
2818 bfe_t *bfe;
2821 if ((bfe = ddi_get_driver_private(dip)) == NULL) {
2830 bfe_grab_locks(bfe);
2831 bfe->bfe_chip_state = BFE_CHIP_RESUME;
2833 bfe_init_vars(bfe);
2835 bfe_chip_reset(bfe);
2836 if (bfe_chip_start(bfe) == DDI_FAILURE) {
2841 bfe_release_locks(bfe);
2844 mac_tx_update(bfe->bfe_machdl);
2853 bfe_t *bfe;
2871 bfe = kmem_zalloc(sizeof (bfe_t), KM_SLEEP);
2872 bfe->bfe_dip = dip;
2873 bfe->bfe_unit = unit;
2875 if (pci_config_setup(dip, &bfe->bfe_conf_handle) != DDI_SUCCESS) {
2883 ret = pci_config_get16(bfe->bfe_conf_handle, PCI_CONF_COMM);
2884 pci_config_put16(bfe->bfe_conf_handle, PCI_CONF_COMM,
2887 ddi_set_driver_private(dip, bfe);
2890 if (bfe_identify_hardware(bfe) == BFE_FAILURE) {
2895 if (bfe_regs_map(bfe) != DDI_SUCCESS) {
2900 (void) bfe_get_chip_config(bfe);
2911 macreg->m_driver = bfe;
2914 macreg->m_src_addr = bfe->bfe_ether_addr;
2920 if ((ret = mac_register(macreg, &bfe->bfe_machdl)) != 0) {
2928 rw_init(&bfe->bfe_rwlock, NULL, RW_DRIVER,
2929 DDI_INTR_PRI(bfe->bfe_intrpri));
2931 if (bfe_add_intr(bfe) != DDI_SUCCESS) {
2936 if (bfe_rings_alloc(bfe) != DDI_SUCCESS) {
2942 bfe->bfe_chip_action = 0;
2943 bfe_init_vars(bfe);
2946 bfe_chip_reset(bfe);
2952 if (ddi_intr_enable(bfe->bfe_intrhdl) != DDI_SUCCESS) {
2960 bfe_remove_intr(bfe);
2962 (void) mac_unregister(bfe->bfe_machdl);
2964 bfe_unmap_regs(bfe);
2966 pci_config_teardown(&bfe->bfe_conf_handle);
2968 kmem_free(bfe, sizeof (bfe_t));
2975 bfe_t *bfe;
2977 bfe = ddi_get_driver_private(devinfo);
2985 bfe_stop_timer(bfe);
2991 if (mac_unregister(bfe->bfe_machdl) != DDI_SUCCESS)
2994 bfe->bfe_machdl = NULL;
2999 bfe_grab_locks(bfe);
3000 bfe_chip_halt(bfe);
3001 bfe_stop_phy(bfe);
3002 bfe_release_locks(bfe);
3004 (void) ddi_intr_disable(bfe->bfe_intrhdl);
3007 bfe_stop_timer(bfe);
3012 if (bfe->bfe_tx_ring.r_flags == BFE_RING_ALLOCATED) {
3014 bfe_buffer_free(&bfe->bfe_tx_ring);
3015 bfe_ring_desc_free(&bfe->bfe_tx_ring);
3018 if (bfe->bfe_rx_ring.r_flags == BFE_RING_ALLOCATED) {
3020 bfe_buffer_free(&bfe->bfe_rx_ring);
3021 bfe_ring_desc_free(&bfe->bfe_rx_ring);
3024 bfe_remove_intr(bfe);
3025 bfe_unmap_regs(bfe);
3026 pci_config_teardown(&bfe->bfe_conf_handle);
3028 mutex_destroy(&bfe->bfe_tx_ring.r_lock);
3029 mutex_destroy(&bfe->bfe_rx_ring.r_lock);
3030 rw_destroy(&bfe->bfe_rwlock);
3032 kmem_free(bfe, sizeof (bfe_t));
3042 bfe_stop_timer(bfe);
3047 bfe_grab_locks(bfe);
3048 bfe_chip_halt(bfe);
3049 bfe_stop_phy(bfe);
3050 bfe->bfe_chip_state = BFE_CHIP_SUSPENDED;
3051 bfe_release_locks(bfe);
3066 bfe_t *bfe;
3068 bfe = ddi_get_driver_private(dev_info);
3070 bfe_chip_halt(bfe);
3071 bfe_stop_phy(bfe);
3072 bfe->bfe_chip_state = BFE_CHIP_QUIESCED;