Lines Matching defs:asc
156 extern int32_t ath_getset(ath_t *asc, mblk_t *mp, uint32_t cmd);
303 ath_setup_desc(ath_t *asc, struct ath_buf *bf)
310 ATH_HAL_SETUPRXDESC(asc->asc_ah, ds,
314 if (asc->asc_rxlink != NULL)
315 *asc->asc_rxlink = bf->bf_daddr;
316 asc->asc_rxlink = &ds->ds_link;
387 ath_buflist_setup(dev_info_t *devinfo, ath_t *asc, list_t *bflist,
398 bf->bf_daddr = asc->asc_desc_dma.cookie.dmac_address +
399 ((uintptr_t)ds - (uintptr_t)asc->asc_desc);
404 asc->asc_dmabuf_size, &ath_desc_accattr, DDI_DMA_STREAMING,
446 ath_desc_free(ath_t *asc)
448 ath_buflist_cleanup(&asc->asc_txbuf_list);
449 ath_buflist_cleanup(&asc->asc_rxbuf_list);
452 ath_free_dma_mem(&asc->asc_desc_dma);
454 kmem_free((void *)asc->asc_vbufptr, asc->asc_vbuflen);
455 asc->asc_vbufptr = NULL;
459 ath_desc_alloc(dev_info_t *devinfo, ath_t *asc)
470 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &asc->asc_desc_dma);
473 asc->asc_desc = (struct ath_desc *)asc->asc_desc_dma.mem_va;
475 ds = asc->asc_desc;
478 asc->asc_desc, asc->asc_desc_dma.alength,
479 asc->asc_desc_dma.cookie.dmac_address));
482 asc->asc_vbuflen = sizeof (struct ath_buf) * (ATH_TXBUF + ATH_RXBUF);
483 bf = (struct ath_buf *)kmem_zalloc(asc->asc_vbuflen, KM_SLEEP);
484 asc->asc_vbufptr = bf;
487 asc->asc_dmabuf_size = roundup(1000 + sizeof (struct ieee80211_frame) +
490 IEEE80211_WEP_CRCLEN), asc->asc_cachelsz);
493 err = ath_buflist_setup(devinfo, asc, &asc->asc_rxbuf_list, &bf, &ds,
496 ath_desc_free(asc);
501 err = ath_buflist_setup(devinfo, asc, &asc->asc_txbuf_list, &bf, &ds,
504 ath_desc_free(asc);
528 ath_rx_handler(ath_t *asc)
530 ieee80211com_t *ic = (ieee80211com_t *)asc;
532 struct ath_hal *ah = asc->asc_ah;
544 mutex_enter(&asc->asc_rxbuflock);
545 bf = list_head(&asc->asc_rxbuf_list);
549 mutex_exit(&asc->asc_rxbuflock);
559 mutex_exit(&asc->asc_rxbuflock);
566 ATH_PA2DESC(asc, ds->ds_link), rs);
568 mutex_exit(&asc->asc_rxbuflock);
571 list_remove(&asc->asc_rxbuf_list, bf);
572 mutex_exit(&asc->asc_rxbuflock);
576 asc->asc_stats.ast_rx_crcerr++;
578 asc->asc_stats.ast_rx_fifoerr++;
580 asc->asc_stats.ast_rx_badcrypt++;
582 asc->asc_stats.ast_rx_phyerr++;
584 asc->asc_stats.ast_rx_phy[phyerr]++;
592 asc->asc_stats.ast_rx_tooshort++;
596 if ((rx_mp = allocb(asc->asc_dmabuf_size, BPRI_MED)) == NULL) {
636 mutex_enter(&asc->asc_rxbuflock);
637 list_insert_tail(&asc->asc_rxbuf_list, bf);
638 mutex_exit(&asc->asc_rxbuflock);
639 ath_setup_desc(asc, bf);
643 ATH_HAL_RXMONITOR(ah, &hal_node_stats, &asc->asc_curchan);
669 ath_tx_start(ath_t *asc, struct ieee80211_node *in, struct ath_buf *bf,
672 ieee80211com_t *ic = (ieee80211com_t *)asc;
674 struct ath_hal *ah = asc->asc_ah;
748 rt = asc->asc_currates;
759 asc->asc_stats.ast_tx_shortpre++;
788 txq = asc->asc_ac2q[WME_AC_VO];
800 txq = asc->asc_ac2q[WME_AC_VO];
811 txq = asc->asc_ac2q[WME_AC_BK];
815 asc->asc_stats.ast_tx_invalid++;
824 asc->asc_stats.ast_tx_noack++;
827 asc->asc_stats.ast_tx_rts++;
957 ath_t *asc = (ath_t *)ic;
958 struct ath_hal *ah = asc->asc_ah;
966 if (!ATH_IS_RUNNING(asc)) {
975 mutex_enter(&asc->asc_txbuflock);
976 bf = list_head(&asc->asc_txbuf_list);
978 list_remove(&asc->asc_txbuf_list, bf);
979 if (list_empty(&asc->asc_txbuf_list)) {
982 asc->asc_stats.ast_tx_qstop++;
984 mutex_exit(&asc->asc_txbuflock);
991 asc->asc_stats.ast_tx_nobuf++;
992 mutex_enter(&asc->asc_resched_lock);
993 asc->asc_resched_needed = B_TRUE;
994 mutex_exit(&asc->asc_resched_lock);
996 asc->asc_stats.ast_tx_nobufmgt++;
1031 asc->asc_stats.ast_tx_mgmt++;
1035 error = ath_tx_start(asc, in, bf, mp);
1040 mutex_enter(&asc->asc_txbuflock);
1041 list_insert_tail(&asc->asc_txbuf_list, bf);
1042 mutex_exit(&asc->asc_txbuflock);
1058 ath_t *asc = arg;
1059 ieee80211com_t *ic = (ieee80211com_t *)asc;
1071 asc->asc_stats.ast_tx_discard++;
1096 ath_tx_processq(ath_t *asc, struct ath_txq *txq)
1098 ieee80211com_t *ic = (ieee80211com_t *)asc;
1099 struct ath_hal *ah = asc->asc_ah;
1136 asc->asc_stats.ast_tx_altrate++;
1137 asc->asc_stats.ast_tx_rssidelta =
1138 ts->ts_rssi - asc->asc_stats.ast_tx_rssi;
1139 asc->asc_stats.ast_tx_rssi = ts->ts_rssi;
1143 asc->asc_stats.ast_tx_xretries++;
1145 asc->asc_stats.ast_tx_fifoerr++;
1147 asc->asc_stats.ast_tx_filtered++;
1152 asc->asc_stats.ast_tx_shortretry += sr;
1153 asc->asc_stats.ast_tx_longretry += lr;
1173 mutex_enter(&asc->asc_txbuflock);
1174 list_insert_tail(&asc->asc_txbuf_list, bf);
1175 mutex_exit(&asc->asc_txbuflock);
1179 mutex_enter(&asc->asc_resched_lock);
1180 if (asc->asc_resched_needed) {
1181 asc->asc_resched_needed = B_FALSE;
1184 mutex_exit(&asc->asc_resched_lock);
1191 ath_tx_handler(ath_t *asc)
1199 if (ATH_TXQ_SETUP(asc, i)) {
1200 (void) ath_tx_processq(asc, &asc->asc_txq[i]);
1209 ath_t *asc = (ath_t *)ic;
1212 ath_rate_update(asc, &an->an_node, 0);
1220 ath_t *asc = (ath_t *)ic;
1226 if (ATH_TXQ_SETUP(asc, i)) {
1227 txq = &asc->asc_txq[i];
1249 ath_t *asc = (ath_t *)ic;
1251 asc->asc_scan_timer = 0;
1253 asc->asc_scan_timer = timeout(ath_next_scan, (void *)asc,
1260 ath_stop_scantimer(ath_t *asc)
1264 while ((asc->asc_scan_timer != 0) && (tmp_id != asc->asc_scan_timer)) {
1265 tmp_id = asc->asc_scan_timer;
1268 asc->asc_scan_timer = 0;
1274 ath_t *asc = (ath_t *)ic;
1275 struct ath_hal *ah = asc->asc_ah;
1289 if (!ATH_IS_RUNNING(asc))
1294 ath_stop_scantimer(asc);
1296 ATH_LOCK(asc);
1300 asc->asc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
1304 ATH_HAL_INTRSET(ah, asc->asc_imask &~ HAL_INT_GLOBAL);
1305 ATH_UNLOCK(asc);
1309 error = ath_chan_set(asc, ic->ic_curchan);
1312 ATH_UNLOCK(asc);
1318 rfilt = ath_calcrxfilter(asc);
1340 ath_beacon_config(asc);
1342 asc->asc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
1343 ATH_HAL_INTRSET(ah, asc->asc_imask);
1348 ath_rate_ctl_reset(asc, nstate);
1350 ATH_UNLOCK(asc);
1355 error = asc->asc_newstate(ic, nstate, arg);
1363 ASSERT(asc->asc_scan_timer == 0);
1364 asc->asc_scan_timer = timeout(ath_next_scan, (void *)asc,
1376 ath_calibrate(ath_t *asc)
1378 struct ath_hal *ah = asc->asc_ah;
1381 asc->asc_stats.ast_per_cal++;
1390 asc->asc_stats.ast_per_rfgain++;
1391 (void) ath_reset(&asc->asc_isc);
1393 if (!ATH_HAL_CALIBRATE(ah, &asc->asc_curchan, &iqcaldone)) {
1396 asc->asc_curchan.channel));
1397 asc->asc_stats.ast_per_calfail++;
1404 ath_t *asc = arg;
1405 ieee80211com_t *ic = &asc->asc_isc;
1408 ATH_LOCK(asc);
1410 if (!ATH_IS_RUNNING(asc)) {
1411 ATH_UNLOCK(asc);
1417 ath_calibrate(asc);
1424 asc->asc_stats.ast_rate_calls ++;
1429 ath_rate_ctl, asc);
1434 ATH_UNLOCK(asc);
1444 ath_t *asc = arg;
1445 ath_tx_handler(asc);
1453 ath_t *asc = (ath_t *)arg;
1454 struct ath_hal *ah = asc->asc_ah;
1456 ieee80211com_t *ic = (ieee80211com_t *)asc;
1458 ATH_LOCK(asc);
1460 if (!ATH_IS_RUNNING(asc)) {
1465 ATH_UNLOCK(asc);
1470 ATH_UNLOCK(asc);
1475 status &= asc->asc_imask;
1477 asc->asc_stats.ast_hardware++;
1480 asc->asc_stats.ast_rxorn++;
1484 asc->asc_stats.ast_rxeol++;
1485 asc->asc_rxlink = NULL;
1488 asc->asc_stats.ast_txurn++;
1493 asc->asc_rx_pend = 1;
1494 ddi_trigger_softintr(asc->asc_softint_id);
1497 if (ddi_taskq_dispatch(asc->asc_tq, ath_tx_proc,
1498 asc, DDI_NOSLEEP) != DDI_SUCCESS) {
1503 ATH_UNLOCK(asc);
1522 ATH_UNLOCK(asc);
1530 ath_t *asc = (ath_t *)data;
1536 ATH_LOCK(asc);
1537 if (asc->asc_rx_pend) { /* Soft interrupt for this driver */
1538 asc->asc_rx_pend = 0;
1539 ATH_UNLOCK(asc);
1540 ath_rx_handler(asc);
1543 ATH_UNLOCK(asc);
1559 ath_stop_locked(ath_t *asc)
1561 ieee80211com_t *ic = (ieee80211com_t *)asc;
1562 struct ath_hal *ah = asc->asc_ah;
1564 ATH_LOCK_ASSERT(asc);
1565 if (!asc->asc_isrunning)
1583 ATH_UNLOCK(asc);
1586 ATH_LOCK(asc);
1588 ath_draintxq(asc);
1589 if (!asc->asc_invalid) {
1590 ath_stoprecv(asc);
1593 asc->asc_rxlink = NULL;
1595 asc->asc_isrunning = 0;
1601 ath_t *asc = arg;
1602 struct ath_hal *ah = asc->asc_ah;
1604 ATH_LOCK(asc);
1605 ath_stop_locked(asc);
1607 asc->asc_invalid = 1;
1608 ATH_UNLOCK(asc);
1612 ath_start_locked(ath_t *asc)
1614 ieee80211com_t *ic = (ieee80211com_t *)asc;
1615 struct ath_hal *ah = asc->asc_ah;
1618 ATH_LOCK_ASSERT(asc);
1627 asc->asc_curchan.channel = ic->ic_curchan->ich_freq;
1628 asc->asc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan);
1630 &asc->asc_curchan, AH_FALSE, &status)) {
1637 (void) ath_startrecv(asc);
1642 asc->asc_imask = HAL_INT_RX | HAL_INT_TX
1645 ATH_HAL_INTRSET(ah, asc->asc_imask);
1652 ath_chan_change(asc, ic->ic_curchan);
1654 asc->asc_isrunning = 1;
1662 ath_t *asc = arg;
1665 ATH_LOCK(asc);
1670 ath_stop_locked(asc);
1672 if ((err = ath_start_locked(asc)) != 0) {
1673 ATH_UNLOCK(asc);
1677 asc->asc_invalid = 0;
1678 ATH_UNLOCK(asc);
1687 ath_t *asc = arg;
1688 struct ath_hal *ah = asc->asc_ah;
1695 ATH_LOCK(asc);
1696 IEEE80211_ADDR_COPY(asc->asc_isc.ic_macaddr, macaddr);
1697 ATH_HAL_SETMAC(ah, asc->asc_isc.ic_macaddr);
1699 (void) ath_reset(&asc->asc_isc);
1700 ATH_UNLOCK(asc);
1707 ath_t *asc = arg;
1708 struct ath_hal *ah = asc->asc_ah;
1711 ATH_LOCK(asc);
1717 asc->asc_promisc = on;
1719 ATH_UNLOCK(asc);
1727 ath_t *asc = arg;
1728 struct ath_hal *ah = asc->asc_ah;
1731 uint32_t *mfilt = asc->asc_mcast_hash;
1733 ATH_LOCK(asc);
1745 asc->asc_mcast_refs[pos]++;
1748 if (--asc->asc_mcast_refs[pos] == 0)
1753 ATH_UNLOCK(asc);
1763 ath_t *asc = arg;
1766 err = ieee80211_setprop(&asc->asc_isc, pr_name, wldp_pr_num,
1769 ATH_LOCK(asc);
1772 if (ATH_IS_RUNNING(asc)) {
1773 ATH_UNLOCK(asc);
1774 (void) ath_m_start(asc);
1775 (void) ieee80211_new_state(&asc->asc_isc,
1777 ATH_LOCK(asc);
1782 ATH_UNLOCK(asc);
1791 ath_t *asc = arg;
1794 err = ieee80211_getprop(&asc->asc_isc, pr_name, wldp_pr_num,
1804 ath_t *asc = arg;
1806 ieee80211_propinfo(&asc->asc_isc, pr_name, wldp_pr_num, mph);
1812 ath_t *asc = arg;
1815 err = ieee80211_ioctl(&asc->asc_isc, wq, mp);
1816 ATH_LOCK(asc);
1818 if (ATH_IS_RUNNING(asc)) {
1819 ATH_UNLOCK(asc);
1820 (void) ath_m_start(asc);
1821 (void) ieee80211_new_state(&asc->asc_isc,
1823 ATH_LOCK(asc);
1826 ATH_UNLOCK(asc);
1832 ath_t *asc = arg;
1833 ieee80211com_t *ic = (ieee80211com_t *)asc;
1837 ATH_LOCK(asc);
1844 *val = asc->asc_stats.ast_tx_nobuf +
1845 asc->asc_stats.ast_tx_nobufmgt;
1848 *val = asc->asc_stats.ast_rx_tooshort;
1864 *val = asc->asc_stats.ast_tx_fifoerr +
1865 asc->asc_stats.ast_tx_xretries +
1866 asc->asc_stats.ast_tx_discard;
1869 *val = asc->asc_stats.ast_tx_xretries;
1872 *val = asc->asc_stats.ast_rx_crcerr;
1875 *val = asc->asc_stats.ast_rx_badcrypt;
1885 ATH_UNLOCK(asc);
1888 ATH_UNLOCK(asc);
1891 ATH_UNLOCK(asc);
1897 ath_pci_setup(ath_t *asc)
1904 ASSERT(asc != NULL);
1905 command = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_COMM);
1907 pci_config_put16(asc->asc_cfg_handle, PCI_CONF_COMM, command);
1908 command = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_COMM);
1928 ath_t *asc;
1931 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo));
1932 if (asc == NULL) {
1938 ATH_LOCK(asc);
1943 if (ath_pci_setup(asc) != 0) {
1946 ATH_UNLOCK(asc);
1950 if (!asc->asc_invalid)
1951 ret = ath_start_locked(asc);
1952 ATH_UNLOCK(asc);
1960 ath_t *asc;
1994 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo));
1995 ic = (ieee80211com_t *)asc;
1996 asc->asc_dev = devinfo;
1998 mutex_init(&asc->asc_genlock, NULL, MUTEX_DRIVER, NULL);
1999 mutex_init(&asc->asc_txbuflock, NULL, MUTEX_DRIVER, NULL);
2000 mutex_init(&asc->asc_rxbuflock, NULL, MUTEX_DRIVER, NULL);
2001 mutex_init(&asc->asc_resched_lock, NULL, MUTEX_DRIVER, NULL);
2003 err = pci_config_setup(devinfo, &asc->asc_cfg_handle);
2010 if (ath_pci_setup(asc) != 0)
2017 csz = pci_config_get8(asc->asc_cfg_handle, PCI_CONF_CACHE_LINESZ);
2025 pci_config_put8(asc->asc_cfg_handle, PCI_CONF_CACHE_LINESZ,
2028 asc->asc_cachelsz = csz << 2;
2029 vendor_id = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_VENID);
2030 device_id = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_DEVID);
2038 pci_config_put8(asc->asc_cfg_handle, PCI_CONF_LATENCY_TIMER, 0xa8);
2039 val = pci_config_get32(asc->asc_cfg_handle, 0x40);
2041 pci_config_put32(asc->asc_cfg_handle, 0x40, val & 0xffff00ff);
2044 ®s, 0, 0, &ath_reg_accattr, &asc->asc_io_handle);
2053 ah = ath_hal_attach(device_id, asc, 0, regs, &status);
2064 asc->asc_ah = ah;
2097 asc->asc_mrretry = ATH_HAL_SETUPXTXDESC(ah, NULL, 0, 0, 0, 0, 0, 0);
2100 asc->asc_mrretry));
2105 asc->asc_keymax = ATH_HAL_KEYCACHESIZE(ah);
2106 if (asc->asc_keymax > sizeof (asc->asc_keymap) * NBBY) {
2109 sizeof (asc->asc_keymap) * NBBY, asc->asc_keymax));
2110 asc->asc_keymax = sizeof (asc->asc_keymap) * NBBY;
2116 for (i = 0; i < asc->asc_keymax; i++)
2127 asc->asc_have11g = 0;
2130 err = ath_getchannels(asc, ath_countrycode, AH_FALSE, AH_TRUE);
2137 ath_rate_setup(asc, IEEE80211_MODE_11A);
2138 ath_rate_setup(asc, IEEE80211_MODE_11B);
2139 ath_rate_setup(asc, IEEE80211_MODE_11G);
2140 ath_rate_setup(asc, IEEE80211_MODE_TURBO_A);
2143 ath_setcurmode(asc, IEEE80211_MODE_11A);
2145 err = ath_desc_alloc(devinfo, asc);
2152 if ((asc->asc_tq = ddi_taskq_create(devinfo, "ath_taskq", 1,
2157 if (ath_txq_setup(asc))
2167 if (asc->asc_have11g)
2202 asc->asc_splitmic = 1;
2207 asc->asc_hasclrkey = ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_CLR);
2214 setbit(asc->asc_keymap, i);
2215 setbit(asc->asc_keymap, i+64);
2216 if (asc->asc_splitmic) {
2217 setbit(asc->asc_keymap, i+32);
2218 setbit(asc->asc_keymap, i+32+64);
2237 asc->asc_newstate = ic->ic_newstate;
2251 asc->asc_rx_pend = 0;
2254 &asc->asc_softint_id, NULL, 0, ath_softint_handler, (caddr_t)asc);
2261 if (ddi_get_iblock_cookie(devinfo, 0, &asc->asc_iblock)
2269 (caddr_t)asc) != DDI_SUCCESS) {
2290 macp->m_driver = asc;
2317 asc->asc_invalid = 1;
2318 asc->asc_isrunning = 0;
2319 asc->asc_promisc = B_FALSE;
2320 bzero(asc->asc_mcast_refs, sizeof (asc->asc_mcast_refs));
2321 bzero(asc->asc_mcast_hash, sizeof (asc->asc_mcast_hash));
2324 ddi_remove_intr(devinfo, 0, asc->asc_iblock);
2326 ddi_remove_softintr(asc->asc_softint_id);
2330 ath_desc_free(asc);
2331 if (asc->asc_tq)
2332 ddi_taskq_destroy(asc->asc_tq);
2334 ah->ah_detach(asc->asc_ah);
2336 ddi_regs_map_free(&asc->asc_io_handle);
2338 pci_config_teardown(&asc->asc_cfg_handle);
2340 asc->asc_invalid = 1;
2341 mutex_destroy(&asc->asc_txbuflock);
2343 if (ATH_TXQ_SETUP(asc, i)) {
2344 struct ath_txq *txq = &asc->asc_txq[i];
2348 mutex_destroy(&asc->asc_rxbuflock);
2349 mutex_destroy(&asc->asc_genlock);
2350 mutex_destroy(&asc->asc_resched_lock);
2360 ath_suspend(ath_t *asc)
2362 ATH_LOCK(asc);
2363 ath_stop_locked(asc);
2364 ATH_UNLOCK(asc);
2373 ath_t *asc;
2375 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo));
2376 ASSERT(asc != NULL);
2383 return (ath_suspend(asc));
2389 if (mac_disable(asc->asc_isc.ic_mach) != 0)
2392 ath_stop_scantimer(asc);
2395 ATH_HAL_INTRSET(asc->asc_ah, 0);
2400 (void) mac_unregister(asc->asc_isc.ic_mach);
2403 ddi_remove_intr(devinfo, 0, asc->asc_iblock);
2404 ddi_remove_softintr(asc->asc_softint_id);
2417 ieee80211_detach(&asc->asc_isc);
2418 ath_desc_free(asc);
2419 ddi_taskq_destroy(asc->asc_tq);
2420 ath_txq_cleanup(asc);
2421 asc->asc_ah->ah_detach(asc->asc_ah);
2424 ddi_regs_map_free(&asc->asc_io_handle);
2425 pci_config_teardown(&asc->asc_cfg_handle);
2428 mutex_destroy(&asc->asc_rxbuflock);
2429 mutex_destroy(&asc->asc_genlock);
2430 mutex_destroy(&asc->asc_resched_lock);
2451 ath_t *asc;
2455 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo));
2457 if (asc == NULL || (ah = asc->asc_ah) == NULL)
2469 if (ATH_TXQ_SETUP(asc, i)) {
2470 ATH_HAL_STOPTXDMA(ah, asc->asc_txq[i].axq_qnum);