Lines Matching defs:ah
29 ath9k_hw_write_regs(struct ath_hal *ah, uint32_t modesIndex, uint32_t freqIndex,
32 struct ath_hal_5416 *ahp = AH5416(ah);
39 ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan)
48 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
69 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
72 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
75 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
86 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
102 REG_WRITE(ah, AR_PHY(0x37), reg32);
104 ah->ah_curchan = chan;
106 AH5416(ah)->ah_curchanRadIndex = -1;
112 ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
120 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
123 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
134 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
137 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
140 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
158 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
173 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
175 ah->ah_curchan = chan;
177 AH5416(ah)->ah_curchanRadIndex = -1;
209 ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan,
212 struct ath_hal_5416 *ahp = AH5416(ah);
220 if (AR_SREV_9280_10_OR_LATER(ah))
223 eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV);
243 ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2);
244 db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2);
250 ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5);
251 db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5);
283 ath9k_hw_rfdetach(struct ath_hal *ah)
285 struct ath_hal_5416 *ahp = AH5416(ah);
336 ath9k_hw_init_rf(struct ath_hal *ah, int *status)
338 struct ath_hal_5416 *ahp = AH5416(ah);
340 if (!AR_SREV_9280_10_OR_LATER(ah)) {
404 ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan)
408 struct ath_hal_5416 *ahp = AH5416(ah);
431 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
445 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
447 REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
448 (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
449 | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));