Lines Matching refs:ah
250 arn_iowrite32(struct ath_hal *ah, uint32_t reg_offset, uint32_t val)
252 struct arn_softc *sc = ah->ah_sc;
253 if (ah->ah_config.serialize_regmode == SER_REG_MODE_ON) {
265 arn_ioread32(struct ath_hal *ah, uint32_t reg_offset)
268 struct arn_softc *sc = ah->ah_sc;
269 if (ah->ah_config.serialize_regmode == SER_REG_MODE_ON) {
560 struct ath_hal *ah = sc->sc_ah;
564 (void) ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
566 (void) ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
678 struct ath_hal *ah = sc->sc_ah;
685 /* Fill in ah->ah_channels */
686 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (uint32_t *)&nchan,
689 uint32_t rd = ah->ah_currentRD;
701 c = &ah->ah_channels[i];
703 index = ath9k_hw_mhz2ieee(ah, c->channel, c->channelFlags);
838 struct ath_hal *ah = sc->sc_ah;
863 (void) ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
881 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
887 ath9k_hw_mhz2ieee(ah, hchan->channel,
918 (void) ath9k_hw_set_interrupts(ah, sc->sc_imask);
936 struct ath_hal *ah = sc->sc_ah;
972 ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
990 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
991 ah->ah_curchan);
997 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
1001 ath9k_hw_getchan_noise(ah,
1002 ah->ah_curchan);
1007 ah->ah_curchan->channel,
1008 ah->ah_curchan->channelFlags,
1014 ah->ah_curchan->channel,
1015 ah->ah_curchan->channelFlags));
1058 struct ath_hal *ah = sc->sc_ah;
1073 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
1084 (void) ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
1124 (void) ath9k_hw_updatetxtriglevel(ah, B_TRUE);
1150 (void) ath9k_hw_set_interrupts(ah, 0);
1156 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
1157 (void) ath9k_hw_set_interrupts(ah, sc->sc_imask);
1167 if (!(ah->ah_caps.hw_caps &
1173 ath9k_hw_setrxabort(ah, 0);
1240 struct ath_hal *ah = sc->sc_ah;
1244 (void) ath9k_hw_set_interrupts(ah, 0);
1248 if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, sc->tx_chan_width,
1272 (void) ath9k_hw_set_interrupts(ah, sc->sc_imask);
1392 struct ath_hal *ah = sc->sc_ah;
1425 (ah, sc->sc_imask &~ ATH9K_INT_GLOBAL);
1429 (void) ath9k_hw_stoptxdma(ah, sc->sc_beaconq);
1483 ath9k_hw_setrxfilter(ah, rfilt);
1486 ath9k_hw_write_associd(ah, bssid, in->in_associd);
1488 ath9k_hw_write_associd(ah, bssid, 0);
1493 if (ath9k_hw_keyisvalid(ah, (uint16_t)i))
1494 (void) ath9k_hw_keysetmac(ah, (uint16_t)i,
1507 (void) ath9k_hw_stoptxdma(ah, sc->sc_beaconq);
1559 (void) ath9k_hw_set_interrupts(ah, sc->sc_imask);
1881 struct ath_hal *ah = sc->sc_ah;
1888 (void) ath9k_hw_keyreset(ah, keyix);
1894 (void) ath9k_hw_keyreset(ah, keyix+32); /* RX key */
1932 struct ath_hal *ah = sc->sc_ah;
1940 return (ath9k_hw_set_keycache_entry(ah, k->wk_keyix, hk,
1950 return (ath9k_hw_set_keycache_entry(ah, k->wk_keyix, hk,
1958 if (!(ath9k_hw_set_keycache_entry(ah, k->wk_keyix, hk, NULL,
1969 return (ath9k_hw_set_keycache_entry(ah, k->wk_keyix, hk, mac, B_FALSE));
2022 struct ath_hal *ah = ((struct arn_softc *)ic)->sc_ah;
2025 (void) ath9k_hw_setslottime(ah, ATH9K_SLOT_TIME_9);
2027 (void) ath9k_hw_setslottime(ah, ATH9K_SLOT_TIME_20);
2159 struct ath_hal *ah = sc->sc_ah;
2180 (void) ath9k_hw_set_interrupts(ah, 0);
2185 (void) ath9k_hw_phy_disable(ah);
2314 struct ath_hal *ah = sc->sc_ah;
2319 rfilt = ath9k_hw_getrxfilter(ah);
2325 ath9k_hw_setrxfilter(ah, rfilt);
2336 struct ath_hal *ah = sc->sc_ah;
2359 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
2369 struct ath_hal *ah = sc->sc_ah;
2379 (void) ath9k_hw_setmac(ah, sc->sc_isc.ic_macaddr);
2556 struct ath_hal *ah;
2559 ah = sc->sc_ah;
2561 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
2564 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
2567 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
2570 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
2573 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
2655 struct ath_hal *ah = sc->sc_ah;
2659 (void) ath9k_hw_get_txq_props(ah, txq->axq_qnum, &qi);
2703 if (!ath9k_hw_set_txq_props(ah, txq->axq_qnum, &qi)) {
2710 (void) ath9k_hw_resettxqueue(ah, txq->axq_qnum);
2801 struct ath_hal *ah;
2871 ah = ath9k_hw_attach(device_id, sc, sc->mem, &status);
2872 if (ah == NULL) {
2878 sc->sc_ah = ah;
2880 ath9k_hw_getmac(ah, ic->ic_macaddr);
2883 sc->sc_keymax = ah->ah_caps.keycache_size;
2896 (void) ath9k_hw_keyreset(ah, (uint16_t)i);
2961 sc->sc_beaconq = arn_beaconq_setup(ah);
3014 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
3035 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
3037 ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
3039 ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
3044 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
3045 (void) ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
3052 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
3067 (void) ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, B_TRUE, NULL);
3068 sc->sc_defant = ath9k_hw_getdefantenna(ah);
3070 ath9k_hw_getmac(ah, sc->sc_myaddr);
3071 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
3072 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
3074 (void) ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
3079 (void) ath9k_hw_setslottime(ah, ATH9K_SLOT_TIME_9);
3245 arn_mac_bb_name(ah->ah_macVersion),
3246 ah->ah_macRev,
3247 arn_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
3248 ah->ah_phyRev,
3268 ath9k_hw_detach(ah);
3413 struct ath_hal *ah;
3417 if (sc == NULL || (ah = sc->sc_ah) == NULL)
3423 (void) ath9k_hw_set_interrupts(ah, 0);
3430 (void) ath9k_hw_stoptxdma(ah, sc->sc_txq[i].axq_qnum);
3436 ath9k_hw_stoppcurecv(ah);
3437 ath9k_hw_setrxfilter(ah, 0);
3438 (void) ath9k_hw_stopdmarecv(ah);
3444 (void) ath9k_hw_phy_disable(ah);