Cross Reference: /illumos-gate/usr/src/uts/common/io/arn/arn

Lines Matching refs:ah
31 ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
34 	struct ath_hal_5416 *ahp = AH5416(ah);
42 	REG_WRITE(ah, AR_IMR_S0,
45 	REG_WRITE(ah, AR_IMR_S1,
48 	REG_RMW_FIELD(ah, AR_IMR_S2,
53 ath9k_hw_dmaRegDump(struct ath_hal *ah)
60 	REG_WRITE(ah, AR_MACMISC,
71 		val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof (uint32_t)));
120 	    REG_READ(ah, AR_OBS_BUS_1)));
122 	    "AR_CR 0x%x \n", REG_READ(ah, AR_CR)));
126 ath9k_hw_gettxbuf(struct ath_hal *ah, uint32_t q)
128 	return (REG_READ(ah, AR_QTXDP(q)));
132 ath9k_hw_puttxbuf(struct ath_hal *ah, uint32_t q, uint32_t txdp)
134 	REG_WRITE(ah, AR_QTXDP(q), txdp);
140 ath9k_hw_txstart(struct ath_hal *ah, uint32_t q)
145 	REG_WRITE(ah, AR_Q_TXE, 1 << q);
151 ath9k_hw_numtxpending(struct ath_hal *ah, uint32_t q)
155 	npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
158 		if (REG_READ(ah, AR_Q_TXE) & (1 << q))
166 ath9k_hw_updatetxtriglevel(struct ath_hal *ah, boolean_t bIncTrigLevel)
168 	struct ath_hal_5416 *ahp = AH5416(ah);
172 	if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)
175 	omask = ath9k_hw_set_interrupts(ah,
178 	txcfg = REG_READ(ah, AR_TXCFG);
187 		REG_WRITE(ah, AR_TXCFG,
190 	(void) ath9k_hw_set_interrupts(ah, omask);
192 	ah->ah_txTrigLevel = (uint16_t)newLevel; /* ??? */
198 ath9k_hw_stoptxdma(struct ath_hal *ah, uint32_t q)
202 	REG_WRITE(ah, AR_Q_TXD, 1 << q);
205 		if (ath9k_hw_numtxpending(ah, q) == 0)
210 	if (ath9k_hw_numtxpending(ah, q)) {
213 		    __func__, ath9k_hw_numtxpending(ah, q), q));
216 			tsfLow = REG_READ(ah, AR_TSF_L32);
217 			REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR));
218 			REG_WRITE(ah, AR_QUIET_PERIOD, 100);
219 			REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
220 			REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
222 			if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
230 		REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
233 		REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
237 		while (ath9k_hw_numtxpending(ah, q)) {
248 		REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
251 	REG_WRITE(ah, AR_Q_TXD, 0);
258 ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
288 ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
300 ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
323 		(void) ath9k_hw_updatetxtriglevel(ah, B_TRUE);
341 		(void) ath9k_hw_updatetxtriglevel(ah, B_TRUE);
345 		(void) ath9k_hw_updatetxtriglevel(ah, B_TRUE);
388 ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
393 	struct ath_hal_5416 *ahp = AH5416(ah);
416 	if (AR_SREV_9285(ah)) {
427 ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
487 ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
499 ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
515 ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
526 ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
535 ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
546 ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
558 ath9k_hw_gettxintrtxqs(struct ath_hal *ah, uint32_t *txqs)
560 	struct ath_hal_5416 *ahp = AH5416(ah);
567 ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
571 	struct ath_hal_5416 *ahp = AH5416(ah);
572 	struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
639 ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
642 	struct ath_hal_5416 *ahp = AH5416(ah);
643 	struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
678 ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
681 	struct ath_hal_5416 *ahp = AH5416(ah);
683 	struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
744 		(void) ath9k_hw_set_txq_props(ah, q, qinfo);
751 ath9k_hw_releasetxqueue(struct ath_hal *ah, uint32_t q)
753 	struct ath_hal_5416 *ahp = AH5416(ah);
754 	struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
779 	ath9k_hw_set_txq_interrupts(ah, qi);
785 ath9k_hw_resettxqueue(struct ath_hal *ah, uint32_t q)
787 	struct ath_hal_5416 *ahp = AH5416(ah);
788 	struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
789 	struct ath9k_channel *chan = ah->ah_curchan;
823 	REG_WRITE(ah, AR_DLCL_IFS(q),
828 	REG_WRITE(ah, AR_DRETRY_LIMIT(q),
833 	REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
834 	REG_WRITE(ah, AR_DMISC(q),
838 		REG_WRITE(ah, AR_QCBRCFG(q),
841 		REG_WRITE(ah, AR_QMISC(q),
842 		    REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR |
847 		REG_WRITE(ah, AR_QRDYTIMECFG(q),
852 	REG_WRITE(ah, AR_DCHNTIME(q),
858 		REG_WRITE(ah, AR_QMISC(q),
859 		    REG_READ(ah, AR_QMISC(q)) |
865 		REG_WRITE(ah, AR_DMISC(q),
866 		    REG_READ(ah, AR_DMISC(q)) |
870 		REG_WRITE(ah, AR_DMISC(q),
871 		    REG_READ(ah, AR_DMISC(q)) |
876 		REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) |
881 		REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
888 		REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) |
893 		    (ah->ah_config.sw_beacon_response_time -
894 		    ah->ah_config.dma_beacon_response_time) -
895 		    ah->ah_config.additional_swba_backoff) * 1024;
896 		REG_WRITE(ah, AR_QRDYTIMECFG(q),
898 		REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
903 		REG_WRITE(ah, AR_QMISC(q),
904 		    REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
907 		REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
915 		REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) |
941 	ath9k_hw_set_txq_interrupts(ah, qi);
948 ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
980 	ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
1016 ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
1020 	struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
1034 ath9k_hw_setrxabort(struct ath_hal *ah, boolean_t set)
1039 		REG_SET_BIT(ah, AR_DIAG_SW,
1042 		if (!ath9k_hw_wait(ah, AR_OBS_BUS_1,
1044 			REG_CLR_BIT(ah, AR_DIAG_SW,
1047 			reg = REG_READ(ah, AR_OBS_BUS_1);
1056 		REG_CLR_BIT(ah, AR_DIAG_SW,
1064 ath9k_hw_putrxbuf(struct ath_hal *ah, uint32_t rxdp)
1066 	REG_WRITE(ah, AR_RXDP, rxdp);
1070 ath9k_hw_rxena(struct ath_hal *ah)
1072 	REG_WRITE(ah, AR_CR, AR_CR_RXE);
1076 ath9k_hw_startpcureceive(struct ath_hal *ah)
1078 	ath9k_enable_mib_counters(ah);
1080 	ath9k_ani_reset(ah);
1082 	REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1086 ath9k_hw_stoppcurecv(struct ath_hal *ah)
1088 	REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1090 	ath9k_hw_disable_mib_counters(ah);
1094 ath9k_hw_stopdmarecv(struct ath_hal *ah)
1096 	REG_WRITE(ah, AR_CR, AR_CR_RXD);
1098 	if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
1102 		    REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)));