Lines Matching refs:ds
258 ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
262 struct ar5416_desc *ads = AR5416DESC(ds);
288 ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
290 struct ar5416_desc *ads = AR5416DESC(ds);
300 ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
302 struct ar5416_desc *ads = AR5416DESC(ds);
307 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
308 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
309 ds->ds_txstat.ts_status = 0;
310 ds->ds_txstat.ts_flags = 0;
314 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
318 ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT;
322 ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO;
327 ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP;
332 ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
337 ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR;
340 ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN;
344 ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
348 ds->ds_txstat.ts_flags |= ATH9K_TX_BA;
349 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
350 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
353 ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
354 switch (ds->ds_txstat.ts_rateindex) {
356 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
359 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
362 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
365 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
369 ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
370 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
371 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
372 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
373 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
374 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
375 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
376 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
377 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
378 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
379 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
380 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
381 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
382 ds->ds_txstat.ts_antenna = 1;
388 ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
392 struct ar5416_desc *ads = AR5416DESC(ds);
427 ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
434 struct ar5416_desc *ads = AR5416DESC(ds);
487 ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
490 struct ar5416_desc *ads = AR5416DESC(ds);
499 ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
502 struct ar5416_desc *ads = AR5416DESC(ds);
515 ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
517 struct ar5416_desc *ads = AR5416DESC(ds);
526 ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
528 struct ar5416_desc *ads = AR5416DESC(ds);
535 ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
538 struct ar5416_desc *ads = AR5416DESC(ds);
546 ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
549 struct ar5416_desc *ads = AR5416DESC(ds);
948 ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
954 struct ar5416_desc *adsp = AR5416DESC(ds);
962 ds->ds_rxstat.rs_status = 0;
963 ds->ds_rxstat.rs_flags = 0;
965 ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
966 ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp;
968 ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
969 ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
970 ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
971 ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
972 ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
973 ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
974 ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
976 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
978 ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID;
980 ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
981 ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
983 ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
984 ds->ds_rxstat.rs_moreaggr =
986 ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
987 ds->ds_rxstat.rs_flags =
989 ds->ds_rxstat.rs_flags |=
993 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
995 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST;
997 ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY;
1001 ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
1003 ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
1005 ds->ds_rxstat.rs_phyerr = (uint8_t)phyerr; /* LINT */
1007 ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT;
1009 ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
1016 ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
1019 struct ar5416_desc *ads = AR5416DESC(ds);