Lines Matching refs:ah
47 static boolean_t ath9k_hw_set_reset_reg(struct ath_hal *ah, uint32_t type);
48 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
50 static uint32_t ath9k_hw_ini_fixup(struct ath_hal *ah,
53 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
55 static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
61 ath9k_hw_mac_usec(struct ath_hal *ah, uint32_t clks)
63 if (ah->ah_curchan != NULL)
65 CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)]);
71 ath9k_hw_mac_to_usec(struct ath_hal *ah, uint32_t clks)
73 struct ath9k_channel *chan = ah->ah_curchan;
76 return (ath9k_hw_mac_usec(ah, clks) / 2);
78 return (ath9k_hw_mac_usec(ah, clks));
82 ath9k_hw_mac_clks(struct ath_hal *ah, uint32_t usecs)
84 if (ah->ah_curchan != NULL)
85 return (usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
86 ah->ah_curchan)]);
92 ath9k_hw_mac_to_clks(struct ath_hal *ah, uint32_t usecs)
94 struct ath9k_channel *chan = ah->ah_curchan;
97 return (ath9k_hw_mac_clks(ah, usecs) * 2);
99 return (ath9k_hw_mac_clks(ah, usecs));
104 ath9k_hw_chan2wmode(struct ath_hal *ah, const struct ath9k_channel *chan)
115 ath9k_hw_wait(struct ath_hal *ah, uint32_t reg, uint32_t mask, uint32_t val)
120 if ((REG_READ(ah, reg) & mask) == val)
127 reg, REG_READ(ah, reg), mask, val));
146 ath9k_get_channel_edges(struct ath_hal *ah,
149 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
165 ath9k_hw_computetxtime(struct ath_hal *ah,
187 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
195 } else if (ah->ah_curchan &&
196 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
223 ath9k_hw_mhz2ieee(struct ath_hal *ah, uint32_t freq, uint32_t flags)
233 if (ath9k_regd_is_public_safety_sku(ah) &&
248 if (ath9k_regd_is_public_safety_sku(ah) &&
264 ath9k_hw_get_channel_centers(struct ath_hal *ah,
269 struct ath_hal_5416 *ahp = AH5416(ah);
300 ath9k_hw_read_revisions(struct ath_hal *ah)
304 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
307 val = REG_READ(ah, AR_SREV);
308 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
309 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
310 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
312 if (!AR_SREV_9100(ah))
313 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
315 ah->ah_macRev = val & AR_SREV_REVISION;
317 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
318 ah->ah_isPciExpress = B_TRUE;
323 ath9k_hw_get_radiorev(struct ath_hal *ah)
328 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
331 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
332 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
341 ath9k_hw_disablepcie(struct ath_hal *ah)
343 if (!AR_SREV_9100(ah))
346 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
347 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
348 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
349 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
350 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
351 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
352 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
353 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
354 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
356 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
360 ath9k_hw_chip_test(struct ath_hal *ah)
372 regHold[i] = REG_READ(ah, addr);
375 REG_WRITE(ah, addr, wrData);
376 rdData = REG_READ(ah, addr);
389 REG_WRITE(ah, addr, wrData);
390 rdData = REG_READ(ah, addr);
401 REG_WRITE(ah, regAddr[i], regHold[i]);
429 ath9k_hw_set_defaults(struct ath_hal *ah)
433 ah->ah_config.dma_beacon_response_time = 2;
434 ah->ah_config.sw_beacon_response_time = 10;
435 ah->ah_config.additional_swba_backoff = 0;
436 ah->ah_config.ack_6mb = 0x0;
437 ah->ah_config.cwm_ignore_extcca = 0;
438 ah->ah_config.pcie_powersave_enable = 0;
439 ah->ah_config.pcie_l1skp_enable = 0;
440 ah->ah_config.pcie_clock_req = 0;
441 ah->ah_config.pcie_power_reset = 0x100;
442 ah->ah_config.pcie_restore = 0;
443 ah->ah_config.pcie_waen = 0;
444 ah->ah_config.analog_shiftreg = 1;
445 ah->ah_config.ht_enable = 1;
446 ah->ah_config.ofdm_trig_low = 200;
447 ah->ah_config.ofdm_trig_high = 500;
448 ah->ah_config.cck_trig_high = 200;
449 ah->ah_config.cck_trig_low = 100;
450 ah->ah_config.enable_ani = 1;
451 ah->ah_config.noise_immunity_level = 4;
452 ah->ah_config.ofdm_weaksignal_det = 1;
453 ah->ah_config.cck_weaksignal_thr = 0;
454 ah->ah_config.spur_immunity_level = 2;
455 ah->ah_config.firstep_level = 0;
456 ah->ah_config.rssi_thr_high = 40;
457 ah->ah_config.rssi_thr_low = 7;
458 ah->ah_config.diversity_control = 0;
459 ah->ah_config.antenna_switch_swap = 0;
462 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
463 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
466 ah->ah_config.intr_mitigation = 1;
495 struct ath_hal *ah;
506 ah = &ahp->ah;
507 ah->ah_sc = sc;
508 ah->ah_sh = mem;
509 ah->ah_magic = AR5416_MAGIC;
510 ah->ah_countryCode = CTRY_DEFAULT;
511 ah->ah_devid = device_id;
512 ah->ah_subvendorid = 0;
514 ah->ah_flags = 0;
516 ah->ah_macVersion = AR_SREV_VERSION_9100;
517 if (!AR_SREV_9100(ah))
518 ah->ah_flags = AH_USE_EEPROM;
520 ah->ah_powerLimit = MAX_RATE_POWER;
521 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
523 ahp->ah_diversityControl = ah->ah_config.diversity_control;
525 ah->ah_config.antenna_switch_swap;
541 ath9k_hw_rfattach(struct ath_hal *ah)
546 rfStatus = ath9k_hw_init_rf(ah, &ecode);
558 ath9k_hw_rf_claim(struct ath_hal *ah)
562 REG_WRITE(ah, AR_PHY(0), 0x00000007);
564 val = ath9k_hw_get_radiorev(ah);
579 ah->ah_analog5GhzRev));
584 ah->ah_analog5GhzRev = (uint16_t)val;
590 ath9k_hw_init_macaddr(struct ath_hal *ah)
595 struct ath_hal_5416 *ahp = AH5416(ah);
599 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
616 ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
619 struct ath_hal_5416 *ahp = AH5416(ah);
621 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
622 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
646 ath9k_hw_init_txgain_ini(struct ath_hal *ah)
649 struct ath_hal_5416 *ahp = AH5416(ah);
651 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
652 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
672 ath9k_hw_post_attach(struct ath_hal *ah)
676 if (!ath9k_hw_chip_test(ah)) {
682 ecode = ath9k_hw_rf_claim(ah);
686 ecode = ath9k_hw_eeprom_attach(ah);
689 ecode = ath9k_hw_rfattach(ah);
693 if (!AR_SREV_9100(ah)) {
694 ath9k_hw_ani_setup(ah);
695 ath9k_hw_ani_attach(ah);
706 struct ath_hal *ah;
715 ah = &ahp->ah;
717 ath9k_hw_set_defaults(ah);
719 if (ah->ah_config.intr_mitigation != 0)
722 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
729 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
736 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
737 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI ||
738 (AR_SREV_9280(ah) && !ah->ah_isPciExpress)) {
739 ah->ah_config.serialize_regmode =
742 ah->ah_config.serialize_regmode =
748 ah->ah_config.serialize_regmode));
750 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
751 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
752 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
753 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) &&
754 (!AR_SREV_9285(ah))) {
757 ah->ah_macVersion, ah->ah_macRev));
762 if (AR_SREV_9100(ah)) {
765 ah->ah_isPciExpress = B_FALSE;
767 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
769 if (AR_SREV_9160_10_OR_LATER(ah)) {
770 if (AR_SREV_9280_10_OR_LATER(ah)) {
790 if (AR_SREV_9160(ah)) {
791 ah->ah_config.enable_ani = 1;
796 if (AR_SREV_9280_10_OR_LATER(ah)) {
803 ah->ah_macVersion, ah->ah_macRev));
805 if (AR_SREV_9285_12_OR_LATER(ah)) {
812 if (ah->ah_config.pcie_clock_req) {
823 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
830 if (ah->ah_config.pcie_clock_req) {
841 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
848 if (ah->ah_config.pcie_clock_req) {
862 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
869 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
899 if (AR_SREV_9160_11(ah)) {
907 } else if (AR_SREV_9100_OR_LATER(ah)) {
975 if (ah->ah_isPciExpress)
976 ath9k_hw_configpcipowersave(ah, 0);
978 ath9k_hw_disablepcie(ah);
980 ecode = ath9k_hw_post_attach(ah);
985 if (AR_SREV_9280_20(ah))
986 ath9k_hw_init_rxgain_ini(ah);
989 if (AR_SREV_9280_20(ah))
990 ath9k_hw_init_txgain_ini(ah);
992 if (ah->ah_devid == AR9280_DEVID_PCI) {
1002 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom.def,
1008 if (!ath9k_hw_fill_cap_info(ah)) {
1014 ecode = ath9k_hw_init_macaddr(ah);
1022 if (AR_SREV_9285(ah))
1023 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
1025 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
1027 ath9k_init_nfcal_hist_buffer(ah);
1029 return (ah);
1040 ath9k_hw_init_bb(struct ath_hal *ah, struct ath9k_channel *chan)
1044 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1050 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1056 ath9k_hw_init_qos(struct ath_hal *ah)
1058 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1059 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1061 REG_WRITE(ah, AR_QOS_NO_ACK,
1066 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1067 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1068 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1069 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1070 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1074 ath9k_hw_init_pll(struct ath_hal *ah, struct ath9k_channel *chan)
1078 if (AR_SREV_9100(ah)) {
1084 if (AR_SREV_9280_10_OR_LATER(ah)) {
1096 if (AR_SREV_9280_20(ah)) {
1107 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1134 REG_WRITE(ah, (uint16_t)(AR_RTC_PLL_CONTROL), pll);
1138 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1142 ath9k_hw_init_chain_masks(struct ath_hal *ah)
1144 struct ath_hal_5416 *ahp = AH5416(ah);
1152 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1156 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1157 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1158 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1165 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1166 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1172 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1174 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1177 if (AR_SREV_9100(ah))
1178 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1179 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1183 ath9k_hw_init_interrupt_masks(struct ath_hal *ah, enum ath9k_opmode opmode)
1185 struct ath_hal_5416 *ahp = AH5416(ah);
1203 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1204 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1206 if (!AR_SREV_9100(ah)) {
1207 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1208 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1209 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1214 ath9k_hw_set_ack_timeout(struct ath_hal *ah, uint32_t us)
1216 struct ath_hal_5416 *ahp = AH5416(ah);
1218 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1225 REG_RMW_FIELD(ah, AR_TIME_OUT,
1226 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1233 ath9k_hw_set_cts_timeout(struct ath_hal *ah, uint32_t us)
1235 struct ath_hal_5416 *ahp = AH5416(ah);
1237 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1244 REG_RMW_FIELD(ah, AR_TIME_OUT,
1245 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1252 ath9k_hw_set_global_txtimeout(struct ath_hal *ah, uint32_t tu)
1254 struct ath_hal_5416 *ahp = AH5416(ah);
1264 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1271 ath9k_hw_init_user_settings(struct ath_hal *ah)
1273 struct ath_hal_5416 *ahp = AH5416(ah);
1279 REG_WRITE(ah, AR_PCU_MISC,
1280 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1282 (void) ath9k_hw_setslottime(ah, ahp->ah_slottime);
1284 (void) ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1286 (void) ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1289 (ah, ahp->ah_globaltxtimeout);
1300 ath9k_hw_detach(struct ath_hal *ah)
1302 if (!AR_SREV_9100(ah))
1303 ath9k_hw_ani_detach(ah);
1305 ath9k_hw_rfdetach(ah);
1306 (void) ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1307 kmem_free(ah, sizeof (struct ath_hal_5416)); /* ???? */
1314 struct ath_hal *ah = NULL;
1323 ah = ath9k_hw_do_attach(device_id, sc, mem, error);
1330 return (ah);
1337 ath9k_hw_override_ini(struct ath_hal *ah, struct ath9k_channel *chan)
1344 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1346 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1347 AR_SREV_9280_10_OR_LATER(ah))
1350 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1354 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1360 switch (ah->ah_devid) {
1395 ath9k_hw_ini_fixup(struct ath_hal *ah, struct ar5416_eeprom_def *pEepData,
1398 struct ath_hal_5416 *ahp = AH5416(ah);
1403 return (ath9k_hw_def_ini_fixup(ah, pEepData, reg, value));
1407 ath9k_hw_process_ini(struct ath_hal *ah,
1412 struct ath_hal_5416 *ahp = AH5416(ah);
1445 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1447 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1449 ath9k_hw_set_addac(ah, chan);
1451 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1473 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1479 REG_WRITE(ah, reg, val);
1482 ah->ah_config.analog_shiftreg) {
1490 if (AR_SREV_9280(ah)) {
1496 if (AR_SREV_9280(ah)) {
1506 REG_WRITE(ah, reg, val);
1509 ah->ah_config.analog_shiftreg) {
1517 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1519 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1525 ath9k_hw_override_ini(ah, chan);
1526 ath9k_hw_set_regs(ah, chan, macmode);
1527 ath9k_hw_init_chain_masks(ah);
1529 status = ath9k_hw_set_txpower(ah, chan,
1530 ath9k_regd_get_ctl(ah, chan),
1531 ath9k_regd_get_antenna_allowed(ah, chan),
1534 (uint32_t)ah->ah_powerLimit));
1542 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1555 ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1565 if (!AR_SREV_9280_10_OR_LATER(ah))
1569 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1573 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1577 ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1579 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1583 ath9k_hw_set_dma(struct ath_hal *ah)
1587 regval = REG_READ(ah, AR_AHB_MODE);
1588 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1590 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1591 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1593 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1595 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1596 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1598 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1600 if (AR_SREV_9285(ah)) {
1601 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1604 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1610 ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1614 val = REG_READ(ah, AR_STA_ID1);
1618 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP |
1620 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1623 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC |
1625 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1629 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1636 ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1656 ath9k_hw_set_delta_slope(struct ath_hal *ah,
1668 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1671 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1674 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1676 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1681 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1684 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1686 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1691 ath9k_hw_set_reset(struct ath_hal *ah, int type)
1696 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1699 if (AR_SREV_9100(ah)) {
1703 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1707 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1708 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1710 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1718 REG_WRITE(ah, (uint16_t)(AR_RTC_RC), rst_flags);
1721 REG_WRITE(ah, (uint16_t)(AR_RTC_RC), 0);
1722 if (!ath9k_hw_wait(ah, (uint16_t)(AR_RTC_RC), AR_RTC_RC_M, 0)) {
1729 if (!AR_SREV_9100(ah))
1730 REG_WRITE(ah, AR_RC, 0);
1732 ath9k_hw_init_pll(ah, NULL);
1734 if (AR_SREV_9100(ah))
1741 ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1743 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1746 REG_WRITE(ah, (uint16_t)(AR_RTC_RESET), 0);
1747 REG_WRITE(ah, (uint16_t)(AR_RTC_RESET), 1);
1749 if (!ath9k_hw_wait(ah,
1760 ath9k_hw_read_revisions(ah);
1762 return (ath9k_hw_set_reset(ah, ATH9K_RESET_WARM));
1766 ath9k_hw_set_reset_reg(struct ath_hal *ah, uint32_t type)
1768 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1773 return (ath9k_hw_set_reset_power_on(ah));
1776 return (ath9k_hw_set_reset(ah, type));
1783 ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1788 struct ath_hal_5416 *ahp = AH5416(ah);
1790 if (AR_SREV_9285_10_OR_LATER(ah))
1791 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1807 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1809 ath9k_hw_set11nmac2040(ah, macmode);
1811 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1812 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1816 ath9k_hw_chip_reset(struct ath_hal *ah,
1819 struct ath_hal_5416 *ahp = AH5416(ah);
1821 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1824 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1829 ath9k_hw_init_pll(ah, chan);
1831 ath9k_hw_set_rfmode(ah, chan);
1837 ath9k_hw_check_chan(struct ath_hal *ah, struct ath9k_channel *chan)
1858 return (ath9k_regd_check_channel(ah, chan));
1862 ath9k_hw_channel_change(struct ath_hal *ah,
1869 if (ath9k_hw_numtxpending(ah, qnum)) {
1878 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1879 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1887 ath9k_hw_set_regs(ah, chan, macmode);
1889 if (AR_SREV_9280_10_OR_LATER(ah)) {
1890 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1896 if (!(ath9k_hw_set_channel(ah, chan))) {
1904 if (ath9k_hw_set_txpower(ah, chan,
1905 ath9k_regd_get_ctl(ah, chan),
1906 ath9k_regd_get_antenna_allowed(ah, chan),
1909 (uint32_t)ah->ah_powerLimit)) != 0) {
1916 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1924 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1927 ath9k_hw_set_delta_slope(ah, chan);
1929 if (AR_SREV_9280_10_OR_LATER(ah))
1930 ath9k_hw_9280_spur_mitigate(ah, chan);
1932 ath9k_hw_spur_mitigate(ah, chan);
1941 ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1972 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1975 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1977 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2002 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
2006 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
2012 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2018 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
2025 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
2055 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
2058 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
2076 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2077 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2110 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2111 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2121 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2122 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2132 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2133 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2143 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2144 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2154 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2155 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2165 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2166 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2176 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2177 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2187 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2188 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2192 ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
2221 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2236 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2242 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2249 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2260 REG_WRITE(ah, AR_PHY_TIMING11, new);
2278 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2279 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2312 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2313 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2323 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2324 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2334 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2335 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2345 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2346 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2356 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2357 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2367 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2368 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2378 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2379 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2389 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2390 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2394 ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2401 struct ath_hal_5416 *ahp = AH5416(ah);
2402 struct ath9k_channel *curchan = ah->ah_curchan;
2412 if (AR_SREV_9280(ah)) {
2417 if (ath9k_hw_check_chan(ah, chan) == NULL) {
2425 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
2433 (void) ath9k_hw_getnf(ah, curchan);
2437 (ah->ah_curchan != NULL) &&
2438 (chan->channel != ah->ah_curchan->channel) &&
2440 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2441 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2442 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2444 if (ath9k_hw_channel_change(ah, chan, macmode)) {
2445 ath9k_hw_loadnf(ah, ah->ah_curchan);
2446 ath9k_hw_start_nfcal(ah);
2451 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2455 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2457 saveLedState = REG_READ(ah, AR_CFG_LED) &
2461 ath9k_hw_mark_phy_inactive(ah);
2463 if (!ath9k_hw_chip_reset(ah, chan)) {
2470 if (AR_SREV_9280(ah)) {
2471 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2473 if (is_set(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2475 ath9k_hw_set_gpio(ah, 9, 0);
2477 ath9k_hw_set_gpio(ah, 9, 1);
2479 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2482 ecode = ath9k_hw_process_ini(ah, chan, macmode);
2489 ath9k_hw_set_delta_slope(ah, chan);
2491 if (AR_SREV_9280_10_OR_LATER(ah))
2492 ath9k_hw_9280_spur_mitigate(ah, chan);
2494 ath9k_hw_spur_mitigate(ah, chan);
2496 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2503 ath9k_hw_decrease_chain_power(ah, chan);
2505 REG_WRITE(ah, AR_STA_ID0, ARN_LE_READ_32(ahp->ah_macaddr));
2506 REG_WRITE(ah, AR_STA_ID1, ARN_LE_READ_16(ahp->ah_macaddr + 4) |
2509 (ah->ah_config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
2511 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2513 REG_WRITE(ah, AR_BSSMSKL, ARN_LE_READ_32(ahp->ah_bssidmask));
2514 REG_WRITE(ah, AR_BSSMSKU, ARN_LE_READ_16(ahp->ah_bssidmask + 4));
2516 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2518 REG_WRITE(ah, AR_BSS_ID0, ARN_LE_READ_32(ahp->ah_bssid));
2519 REG_WRITE(ah, AR_BSS_ID1, ARN_LE_READ_16(ahp->ah_bssid + 4) |
2522 REG_WRITE(ah, AR_ISR, ~0);
2524 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2526 if (AR_SREV_9280_10_OR_LATER(ah)) {
2527 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
2535 if (!(ath9k_hw_set_channel(ah, chan))) {
2544 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2547 for (i = 0; i < ah->ah_caps.total_queues; i++)
2548 (void) ath9k_hw_resettxqueue(ah, i);
2550 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2551 ath9k_hw_init_qos(ah);
2554 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2555 ath9k_enable_rfkill(ah);
2557 ath9k_hw_init_user_settings(ah);
2559 REG_WRITE(ah, AR_STA_ID1,
2560 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2562 ath9k_hw_set_dma(ah);
2564 REG_WRITE(ah, AR_OBS, 8);
2568 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2569 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2572 ath9k_hw_init_bb(ah, chan);
2574 if (!ath9k_hw_init_cal(ah, chan)) {
2581 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2582 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2585 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2587 if (AR_SREV_9100(ah)) {
2589 mask = REG_READ(ah, AR_CFG);
2597 REG_WRITE(ah, AR_CFG, mask);
2600 __func__, REG_READ(ah, AR_CFG)));
2606 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2620 ath9k_hw_keyreset(struct ath_hal *ah, uint16_t entry)
2624 if (entry >= ah->ah_caps.keycache_size) {
2631 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2633 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2634 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2635 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2636 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2637 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2638 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2639 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2640 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2643 ATH9K_IS_MIC_ENABLED(ah)) {
2646 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2647 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2648 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2649 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2653 if (ah->ah_curchan == NULL)
2660 ath9k_hw_keysetmac(struct ath_hal *ah, uint16_t entry, const uint8_t *mac)
2664 if (entry >= ah->ah_caps.keycache_size) {
2682 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2683 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2689 ath9k_hw_set_keycache_entry(struct ath_hal *ah, uint16_t entry,
2692 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2698 struct ath_hal_5416 *ahp = AH5416(ah);
2715 ah->ah_macRev));
2722 if (ATH9K_IS_MIC_ENABLED(ah) &&
2763 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2766 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2767 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2768 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2769 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2770 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2771 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2772 (void) ath9k_hw_keysetmac(ah, entry, mac);
2781 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2782 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2783 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2784 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2785 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2786 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2793 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2794 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2795 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2796 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2797 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2798 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2801 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2802 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2803 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2804 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2806 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2807 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2808 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2809 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2810 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2811 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2813 (void) ath9k_hw_keysetmac(ah, entry, mac);
2816 if (ah->ah_curchan == NULL)
2823 ath9k_hw_keyisvalid(struct ath_hal *ah, uint16_t entry)
2825 if (entry < ah->ah_caps.keycache_size) {
2826 uint32_t val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2836 ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2838 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2840 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2842 if (!AR_SREV_9100(ah))
2843 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2845 REG_CLR_BIT(ah, (uint16_t)(AR_RTC_RESET),
2851 ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2853 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2855 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2858 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2861 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2868 ath9k_hw_set_power_awake(struct ath_hal *ah, int setChip)
2874 if ((REG_READ(ah, AR_RTC_STATUS) &
2876 if (ath9k_hw_set_reset_reg(ah,
2881 if (AR_SREV_9100(ah))
2882 REG_SET_BIT(ah, AR_RTC_RESET,
2885 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2890 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2894 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2907 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2913 ath9k_hw_setpower(struct ath_hal *ah, enum ath9k_power_mode mode)
2915 struct ath_hal_5416 *ahp = AH5416(ah);
2931 status = ath9k_hw_set_power_awake(ah, setChip);
2934 ath9k_set_power_sleep(ah, setChip);
2938 ath9k_set_power_network_sleep(ah, setChip);
2951 ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2953 struct ath_hal_5416 *ahp = AH5416(ah);
2956 if (ah->ah_isPciExpress != B_TRUE)
2959 if (ah->ah_config.pcie_powersave_enable == 2)
2965 if (AR_SREV_9280_20_OR_LATER(ah)) {
2967 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2971 } else if (AR_SREV_9280(ah) &&
2972 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2973 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2974 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2976 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2977 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2978 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2980 if (ah->ah_config.pcie_clock_req)
2981 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2983 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2985 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2986 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2987 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2989 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2993 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2994 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2995 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2996 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2997 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2998 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2999 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3000 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3001 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3002 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3005 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3007 if (ah->ah_config.pcie_waen) {
3008 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
3010 if (AR_SREV_9285(ah))
3011 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
3012 else if (AR_SREV_9280(ah))
3013 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
3015 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
3022 ath9k_hw_intrpend(struct ath_hal *ah)
3026 if (AR_SREV_9100(ah))
3029 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3033 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3043 ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
3047 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3050 struct ath_hal_5416 *ahp = AH5416(ah);
3052 if (!AR_SREV_9100(ah)) {
3053 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3054 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3056 isr = REG_READ(ah, AR_ISR);
3060 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3069 isr = REG_READ(ah, AR_ISR);
3075 isr2 = REG_READ(ah, AR_ISR_S2);
3090 isr = REG_READ(ah, AR_ISR_RAC);
3112 s0_s = REG_READ(ah, AR_ISR_S0_S);
3116 s1_s = REG_READ(ah, AR_ISR_S1_S);
3126 if (!AR_SREV_9100(ah)) {
3128 uint32_t isr5 = REG_READ(ah, AR_ISR_S5_S);
3137 if (AR_SREV_9100(ah))
3162 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3163 REG_WRITE(ah, AR_RC, 0);
3172 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3173 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3180 ath9k_hw_intrget(struct ath_hal *ah)
3182 return (AH5416(ah)->ah_maskReg);
3186 ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
3188 struct ath_hal_5416 *ahp = AH5416(ah);
3191 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3202 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3203 (void) REG_READ(ah, AR_IER);
3204 if (!AR_SREV_9100(ah)) {
3205 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3206 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3208 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3209 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3256 REG_WRITE(ah, AR_IMR, mask);
3257 mask = REG_READ(ah, AR_IMR_S2) &
3266 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3271 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3273 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3277 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3278 if (!AR_SREV_9100(ah)) {
3279 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3281 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3284 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3286 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3298 ath9k_hw_beaconinit(struct ath_hal *ah, uint32_t next_beacon,
3301 struct ath_hal_5416 *ahp = AH5416(ah);
3306 switch (ah->ah_opmode) {
3309 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3310 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3311 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3315 REG_SET_BIT(ah, AR_TXCFG,
3317 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3324 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3325 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3327 ah->ah_config.
3329 REG_WRITE(ah, AR_NEXT_SWBA,
3331 ah->ah_config.
3339 __func__, ah->ah_opmode));
3343 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3344 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3345 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3346 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3351 ath9k_hw_reset_tsf(ah);
3354 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3358 ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3362 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3364 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3366 REG_WRITE(ah, AR_BEACON_PERIOD,
3368 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3371 REG_RMW_FIELD(ah, AR_RSSI_THR,
3397 REG_WRITE(ah, AR_NEXT_DTIM,
3399 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3401 REG_WRITE(ah, AR_SLEEP1,
3410 REG_WRITE(ah, AR_SLEEP2,
3413 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3414 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3416 REG_SET_BIT(ah, AR_TIMER_MODE,
3422 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3428 ath9k_hw_fill_cap_info(struct ath_hal *ah)
3430 struct ath_hal_5416 *ahp = AH5416(ah);
3431 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3434 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3436 ah->ah_currentRD = eeval;
3438 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3439 ah->ah_currentRDExt = eeval;
3441 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3443 if (ah->ah_opmode != ATH9K_M_HOSTAP &&
3444 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3445 if (ah->ah_currentRD == 0x64 ||
3446 ah->ah_currentRD == 0x65)
3447 ah->ah_currentRD += 5;
3448 else if (ah->ah_currentRD == 0x41)
3449 ah->ah_currentRD = 0x43;
3453 ah->ah_currentRD));
3456 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3462 if (ah->ah_config.ht_enable) {
3478 if (ah->ah_config.ht_enable) {
3491 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3492 if ((ah->ah_isPciExpress) ||
3495 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3498 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3501 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3520 if (ah->ah_config.ht_enable)
3546 if (AR_SREV_9280_10_OR_LATER(ah))
3551 if (AR_SREV_9280_10_OR_LATER(ah)) {
3559 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3569 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3570 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3571 ah->ah_rfkill_gpio =
3572 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3573 ah->ah_rfkill_polarity =
3574 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3580 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3581 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3582 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3583 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3584 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3589 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3594 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3610 ath9k_hw_get_num_ant_config(ah, 0);
3613 ath9k_hw_get_num_ant_config(ah, 1);
3619 ath9k_hw_getcapability(struct ath_hal *ah,
3623 struct ath_hal_5416 *ahp = AH5416(ah);
3624 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3657 return ((REG_READ(ah, AR_PHY_CCK_DETECT) &
3667 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3694 *result = ah->ah_powerLimit;
3697 *result = ah->ah_maxPowerLevel;
3700 *result = ah->ah_tpScale;
3711 ath9k_hw_setcapability(struct ath_hal *ah,
3716 struct ath_hal_5416 *ahp = AH5416(ah);
3729 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3734 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3756 ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3771 if (AR_SREV_9280_20_OR_LATER(ah) ||
3773 REG_RMW(ah, addr, (type << gpio_shift),
3776 tmp = REG_READ(ah, addr);
3780 REG_WRITE(ah, addr, tmp);
3785 ath9k_hw_cfg_gpio_input(struct ath_hal *ah, uint32_t gpio)
3789 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3793 REG_RMW(ah,
3800 ath9k_hw_gpio_get(struct ath_hal *ah, uint32_t gpio)
3802 if (gpio >= ah->ah_caps.num_gpio_pins)
3805 if (AR_SREV_9280_10_OR_LATER(ah)) {
3806 return ((MS(REG_READ(ah, AR_GPIO_IN_OUT),
3809 return ((MS(REG_READ(ah,
3816 ath9k_hw_cfg_output(struct ath_hal *ah, uint32_t gpio,
3821 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3825 REG_RMW(ah,
3832 ath9k_hw_set_gpio(struct ath_hal *ah, uint32_t gpio, uint32_t val)
3834 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3840 ath9k_enable_rfkill(struct ath_hal *ah)
3842 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3845 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3848 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3849 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3854 ath9k_hw_select_antconfig(struct ath_hal *ah, uint32_t cfg)
3856 struct ath9k_channel *chan = ah->ah_curchan;
3857 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3865 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3867 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3876 ath9k_hw_getdefantenna(struct ath_hal *ah)
3878 return (REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
3882 ath9k_hw_setantenna(struct ath_hal *ah, uint32_t antenna)
3884 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3889 ath9k_hw_setantennaswitch(struct ath_hal *ah,
3896 struct ath_hal_5416 *ahp = AH5416(ah);
3899 if (AR_SREV_9280(ah)) {
3913 if (ah->ah_caps.tx_chainmask >
3938 ath9k_hw_getrxfilter(struct ath_hal *ah)
3940 uint32_t bits = REG_READ(ah, AR_RX_FILTER);
3941 uint32_t phybits = REG_READ(ah, AR_PHY_ERR);
3952 ath9k_hw_setrxfilter(struct ath_hal *ah, uint32_t bits)
3956 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3963 REG_WRITE(ah, AR_PHY_ERR, phybits);
3966 REG_WRITE(ah, AR_RXCFG,
3967 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3969 REG_WRITE(ah, AR_RXCFG,
3970 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3974 ath9k_hw_phy_disable(struct ath_hal *ah)
3976 return (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM));
3980 ath9k_hw_disable(struct ath_hal *ah)
3982 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3985 return (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD));
3989 ath9k_hw_set_txpowerlimit(struct ath_hal *ah, uint32_t limit)
3991 struct ath9k_channel *chan = ah->ah_curchan;
3994 ah->ah_powerLimit = (uint16_t)min(limit, (uint32_t)MAX_RATE_POWER);
3996 if (ath9k_hw_set_txpower(ah, chan,
3997 ath9k_regd_get_ctl(ah, chan),
3998 ath9k_regd_get_antenna_allowed(ah, chan),
4001 (uint32_t)ah->ah_powerLimit)) != 0)
4008 ath9k_hw_getmac(struct ath_hal *ah, uint8_t *mac)
4010 struct ath_hal_5416 *ahp = AH5416(ah);
4016 ath9k_hw_setmac(struct ath_hal *ah, const uint8_t *mac)
4018 struct ath_hal_5416 *ahp = AH5416(ah);
4026 ath9k_hw_setopmode(struct ath_hal *ah)
4028 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
4032 ath9k_hw_setmcastfilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
4034 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4035 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
4039 ath9k_hw_getbssidmask(struct ath_hal *ah, uint8_t *mask)
4041 struct ath_hal_5416 *ahp = AH5416(ah);
4047 ath9k_hw_setbssidmask(struct ath_hal *ah, const uint8_t *mask)
4049 struct ath_hal_5416 *ahp = AH5416(ah);
4053 REG_WRITE(ah, AR_BSSMSKL, ARN_LE_READ_32(ahp->ah_bssidmask));
4054 REG_WRITE(ah, AR_BSSMSKU, ARN_LE_READ_16(ahp->ah_bssidmask + 4));
4060 ath9k_hw_write_associd(struct ath_hal *ah,
4063 struct ath_hal_5416 *ahp = AH5416(ah);
4068 REG_WRITE(ah, AR_BSS_ID0, ARN_LE_READ_32(ahp->ah_bssid));
4069 REG_WRITE(ah, AR_BSS_ID1, ARN_LE_READ_16(ahp->ah_bssid + 4) |
4074 ath9k_hw_gettsf64(struct ath_hal *ah)
4078 tsf = REG_READ(ah, AR_TSF_U32);
4079 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4085 ath9k_hw_reset_tsf(struct ath_hal *ah)
4090 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
4101 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4105 ath9k_hw_set_tsfadjust(struct ath_hal *ah, uint32_t setting)
4107 struct ath_hal_5416 *ahp = AH5416(ah);
4118 ath9k_hw_setslottime(struct ath_hal *ah, uint32_t us)
4120 struct ath_hal_5416 *ahp = AH5416(ah);
4122 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4129 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4136 ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
4141 !ah->ah_config.cwm_ignore_extcca)
4146 REG_WRITE(ah, AR_2040_MODE, macmode);