Lines Matching defs:ahp
269 struct ath_hal_5416 *ahp = AH5416(ah);
292 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
494 struct ath_hal_5416 *ahp;
497 ahp = (struct ath_hal_5416 *)
499 if (ahp == NULL) {
501 "failed to alloc mem for ahp\n"));
506 ah = &ahp->ah;
522 ahp->ah_atimWindow = 0;
523 ahp->ah_diversityControl = ah->ah_config.diversity_control;
524 ahp->ah_antennaSwitchSwap =
526 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
527 ahp->ah_beaconInterval = 100;
528 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
529 ahp->ah_slottime = (uint32_t)-1;
530 ahp->ah_acktimeout = (uint32_t)-1;
531 ahp->ah_ctstimeout = (uint32_t)-1;
532 ahp->ah_globaltxtimeout = (uint32_t)-1;
533 (void) memcpy(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN);
535 ahp->ah_gBeaconRate = 0;
537 return (ahp);
595 struct ath_hal_5416 *ahp = AH5416(ah);
601 ahp->ah_macaddr[2 * i] = eeval >> 8;
602 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
607 ahp->ah_macaddr));
619 struct ath_hal_5416 *ahp = AH5416(ah);
624 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
629 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
634 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
639 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
649 struct ath_hal_5416 *ahp = AH5416(ah);
655 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
660 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
665 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
705 struct ath_hal_5416 *ahp;
711 ahp = ath9k_hw_newstate(device_id, sc, mem, status);
712 if (ahp == NULL)
715 ah = &ahp->ah;
720 ahp->ah_intrMitigation = B_TRUE;
763 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
764 ahp->ah_suppCals = IQ_MISMATCH_CAL;
771 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
772 ahp->ah_adcGainCalData.calData =
774 ahp->ah_adcDcCalData.calData =
776 ahp->ah_adcDcCalInitData.calData =
779 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
780 ahp->ah_adcGainCalData.calData =
782 ahp->ah_adcDcCalData.calData =
784 ahp->ah_adcDcCalInitData.calData =
787 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
792 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
795 ahp->ah_ani_function = ATH9K_ANI_ALL;
797 ahp->ah_ani_function &=
806 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
809 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
813 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
818 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
824 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
827 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
832 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
836 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
842 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
845 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
849 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
853 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
859 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
864 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
867 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
870 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
873 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
876 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
879 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
882 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
885 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
888 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
891 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
894 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
897 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
900 INIT_INI_ARRAY(&ahp->ah_iniAddac,
904 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
908 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
911 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
914 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
917 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
920 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
923 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
926 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
929 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
932 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
935 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
938 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
941 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
944 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
947 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
950 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
953 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
956 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
959 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
962 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
965 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
968 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
971 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
993 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
995 INI_RA(&ahp->ah_iniModes, i, 0);
997 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
999 = INI_RA(&ahp->ah_iniModes, i, j);
1001 INI_RA(&ahp->ah_iniModes, i, j) =
1002 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom.def,
1031 if (ahp)
1032 ath9k_hw_detach((struct ath_hal *)ahp);
1144 struct ath_hal_5416 *ahp = AH5416(ah);
1147 rx_chainmask = ahp->ah_rxchainmask;
1148 tx_chainmask = ahp->ah_txchainmask;
1185 struct ath_hal_5416 *ahp = AH5416(ah);
1187 ahp->ah_maskReg = AR_IMR_TXERR |
1193 if (ahp->ah_intrMitigation)
1194 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1196 ahp->ah_maskReg |= AR_IMR_RXOK;
1198 ahp->ah_maskReg |= AR_IMR_TXOK;
1201 ahp->ah_maskReg |= AR_IMR_MIB;
1203 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1216 struct ath_hal_5416 *ahp = AH5416(ah);
1222 ahp->ah_acktimeout = (uint32_t)-1;
1227 ahp->ah_acktimeout = us;
1235 struct ath_hal_5416 *ahp = AH5416(ah);
1241 ahp->ah_ctstimeout = (uint32_t)-1;
1246 ahp->ah_ctstimeout = us;
1254 struct ath_hal_5416 *ahp = AH5416(ah);
1261 ahp->ah_globaltxtimeout = (uint32_t)-1;
1265 ahp->ah_globaltxtimeout = tu;
1273 struct ath_hal_5416 *ahp = AH5416(ah);
1276 "--AP ahp->ah_miscMode 0x%x\n", ahp->ah_miscMode));
1278 if (ahp->ah_miscMode != 0)
1280 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1281 if (ahp->ah_slottime != (uint32_t)-1)
1282 (void) ath9k_hw_setslottime(ah, ahp->ah_slottime);
1283 if (ahp->ah_acktimeout != (uint32_t)-1)
1284 (void) ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1285 if (ahp->ah_ctstimeout != (uint32_t)-1)
1286 (void) ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1287 if (ahp->ah_globaltxtimeout != (uint32_t)-1)
1289 (ah, ahp->ah_globaltxtimeout);
1398 struct ath_hal_5416 *ahp = AH5416(ah);
1400 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1412 struct ath_hal_5416 *ahp = AH5416(ah);
1453 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1457 sizeof (uint32_t) * ahp->ah_iniAddac.ia_rows *
1458 ahp->ah_iniAddac.ia_columns;
1460 (void) memcpy(ahp->ah_addac5416_21,
1461 ahp->ah_iniAddac.ia_array, addacSize);
1463 (ahp->ah_addac5416_21)
1464 [31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1466 temp.ia_array = ahp->ah_addac5416_21;
1467 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1468 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1475 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1476 uint32_t reg = INI_RA(&ahp->ah_iniModes, i, 0);
1477 uint32_t val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1492 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex,
1498 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex,
1502 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1503 uint32_t reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1504 uint32_t val = INI_RA(&ahp->ah_iniCommon, i, 1);
1521 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1788 struct ath_hal_5416 *ahp = AH5416(ah);
1804 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1819 struct ath_hal_5416 *ahp = AH5416(ah);
1827 ahp->ah_chipFullSleep = B_FALSE;
2401 struct ath_hal_5416 *ahp = AH5416(ah);
2408 ahp->ah_extprotspacing = extprotspacing;
2409 ahp->ah_txchainmask = txchainmask;
2410 ahp->ah_rxchainmask = rxchainmask;
2413 ahp->ah_txchainmask &= 0x3;
2414 ahp->ah_rxchainmask &= 0x3;
2436 (ahp->ah_chipFullSleep != B_TRUE) &&
2505 REG_WRITE(ah, AR_STA_ID0, ARN_LE_READ_32(ahp->ah_macaddr));
2506 REG_WRITE(ah, AR_STA_ID1, ARN_LE_READ_16(ahp->ah_macaddr + 4) |
2510 ahp->ah_staId1Defaults);
2513 REG_WRITE(ah, AR_BSSMSKL, ARN_LE_READ_32(ahp->ah_bssidmask));
2514 REG_WRITE(ah, AR_BSSMSKU, ARN_LE_READ_16(ahp->ah_bssidmask + 4));
2518 REG_WRITE(ah, AR_BSS_ID0, ARN_LE_READ_32(ahp->ah_bssid));
2519 REG_WRITE(ah, AR_BSS_ID1, ARN_LE_READ_16(ahp->ah_bssid + 4) |
2520 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2546 ahp->ah_intrTxqs = 0;
2566 if (ahp->ah_intrMitigation) {
2579 rx_chainmask = ahp->ah_rxchainmask;
2698 struct ath_hal_5416 *ahp = AH5416(ah);
2774 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2915 struct ath_hal_5416 *ahp = AH5416(ah);
2925 modes[ahp->ah_powerMode],
2935 ahp->ah_chipFullSleep = B_TRUE;
2945 ahp->ah_powerMode = mode;
2953 struct ath_hal_5416 *ahp = AH5416(ah);
2966 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2967 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2968 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
3050 struct ath_hal_5416 *ahp = AH5416(ah);
3098 if (ahp->ah_intrMitigation) {
3113 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3114 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3117 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3118 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3188 struct ath_hal_5416 *ahp = AH5416(ah);
3189 uint32_t omask = ahp->ah_maskReg;
3217 if (ahp->ah_txOkInterruptMask)
3219 if (ahp->ah_txDescInterruptMask)
3221 if (ahp->ah_txErrInterruptMask)
3223 if (ahp->ah_txEolInterruptMask)
3228 if (ahp->ah_intrMitigation)
3267 ahp->ah_maskReg = ints;
3301 struct ath_hal_5416 *ahp = AH5416(ah);
3304 ahp->ah_beaconInterval = beacon_period;
3319 (ahp->ah_atimWindow ? ahp->
3430 struct ath_hal_5416 *ahp = AH5416(ah);
3502 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3623 struct ath_hal_5416 *ahp = AH5416(ah);
3644 return ((ahp->ah_staId1Defaults &
3650 return ((ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3655 return (ahp->ah_hasHwPhyCounters ? 0 : -ENXIO);
3670 return ((ahp->ah_staId1Defaults &
3677 return ((ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3716 struct ath_hal_5416 *ahp = AH5416(ah);
3722 ahp->ah_staId1Defaults |=
3725 ahp->ah_staId1Defaults &=
3738 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3740 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3744 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3746 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3896 struct ath_hal_5416 *ahp = AH5416(ah);
3929 ahp->ah_diversityControl = settings;
4010 struct ath_hal_5416 *ahp = AH5416(ah);
4012 (void) memcpy(mac, ahp->ah_macaddr, 6);
4018 struct ath_hal_5416 *ahp = AH5416(ah);
4020 (void) memcpy(ahp->ah_macaddr, mac, 6);
4041 struct ath_hal_5416 *ahp = AH5416(ah);
4043 (void) memcpy(mask, ahp->ah_bssidmask, 6);
4049 struct ath_hal_5416 *ahp = AH5416(ah);
4051 (void) memcpy(ahp->ah_bssidmask, mask, 6);
4053 REG_WRITE(ah, AR_BSSMSKL, ARN_LE_READ_32(ahp->ah_bssidmask));
4054 REG_WRITE(ah, AR_BSSMSKU, ARN_LE_READ_16(ahp->ah_bssidmask + 4));
4063 struct ath_hal_5416 *ahp = AH5416(ah);
4065 (void) memcpy(ahp->ah_bssid, bssid, 6);
4066 ahp->ah_assocId = assocId;
4068 REG_WRITE(ah, AR_BSS_ID0, ARN_LE_READ_32(ahp->ah_bssid));
4069 REG_WRITE(ah, AR_BSS_ID1, ARN_LE_READ_16(ahp->ah_bssid + 4) |
4107 struct ath_hal_5416 *ahp = AH5416(ah);
4110 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
4112 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
4120 struct ath_hal_5416 *ahp = AH5416(ah);
4126 ahp->ah_slottime = (uint32_t)-1;
4130 ahp->ah_slottime = us;