Lines Matching refs:ah
60 ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
66 regVal = REG_READ(ah, reg) & ~mask;
69 REG_WRITE(ah, reg, regVal);
71 if (ah->ah_config.analog_shiftreg)
131 ath9k_hw_eeprom_read(struct ath_hal *ah, uint32_t off, uint16_t *data)
133 (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
135 if (!ath9k_hw_wait(ah, AR_EEPROM_STATUS_DATA,
141 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
149 ath9k_hw_flash_map(struct ath_hal *ah)
158 ath9k_hw_flash_read(struct ath_hal *ah, uint32_t off, uint16_t *data)
160 *data = FLASH_READ(ah, off);
166 ath9k_hw_nvram_read(struct ath_hal *ah, uint32_t off, uint16_t *data)
168 if (ath9k_hw_use_flash(ah))
169 return (ath9k_hw_flash_read(ah, off, data));
171 return (ath9k_hw_eeprom_read(ah, off, data));
175 ath9k_hw_fill_4k_eeprom(struct ath_hal *ah)
178 struct ath_hal_5416 *ahp = AH5416(ah);
185 if (!ath9k_hw_use_flash(ah)) {
193 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
205 ath9k_hw_fill_def_eeprom(struct ath_hal *ah)
208 struct ath_hal_5416 *ahp = AH5416(ah);
216 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
234 ath9k_hw_fill_eeprom(struct ath_hal *ah)
236 struct ath_hal_5416 *ahp = AH5416(ah);
238 return (ath9k_fill_eeprom[ahp->ah_eep_map](ah));
242 ath9k_hw_check_def_eeprom(struct ath_hal *ah)
244 struct ath_hal_5416 *ahp = AH5416(ah);
251 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
257 if (!ath9k_hw_use_flash(ah)) {
371 ath9k_hw_check_4k_eeprom(struct ath_hal *ah)
374 struct ath_hal_5416 *ahp = AH5416(ah);
383 if (!ath9k_hw_use_flash(ah)) {
385 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
504 ath9k_hw_check_eeprom(struct ath_hal *ah)
506 struct ath_hal_5416 *ahp = AH5416(ah);
508 return (ath9k_check_eeprom[ahp->ah_eep_map](ah));
541 ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hal *ah,
572 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
645 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
653 if (AR_SREV_9280_10_OR_LATER(ah))
712 ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hal *ah,
740 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
813 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
821 if (AR_SREV_9280_10_OR_LATER(ah))
881 ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
894 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
938 ath9k_hw_get_target_powers(struct ath_hal *ah,
951 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1028 ath9k_hw_set_def_power_cal_table(struct ath_hal *ah,
1031 struct ath_hal_5416 *ahp = AH5416(ah);
1054 (uint16_t)(MS(REG_READ(ah, AR_PHY_TPCRG5),
1078 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
1080 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
1082 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
1084 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
1088 if (AR_SREV_5416_V20_OR_LATER(ah) &&
1101 ath9k_hw_get_def_gain_boundaries_pdadcs(ah, chan,
1107 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
1108 REG_WRITE(ah,
1128 REG_WRITE(ah, regOffset, reg32);
1156 ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah,
1159 struct ath_hal_5416 *ahp = AH5416(ah);
1179 pdGainOverlap_t2 = (uint16_t)(MS(REG_READ(ah, AR_PHY_TPCRG5),
1198 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
1200 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
1202 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
1204 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
1208 if (AR_SREV_5416_V20_OR_LATER(ah) &&
1218 ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
1224 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
1225 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
1244 REG_WRITE(ah, regOffset, reg32);
1273 ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah,
1283 struct ath_hal_5416 *ahp = AH5416(ah);
1316 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1335 if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
1337 (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
1360 ath9k_hw_get_legacy_target_powers(ah, chan,
1364 ath9k_hw_get_legacy_target_powers(ah, chan,
1368 ath9k_hw_get_target_powers(ah, chan,
1375 ath9k_hw_get_target_powers(ah, chan,
1379 ath9k_hw_get_legacy_target_powers(ah, chan,
1383 ath9k_hw_get_legacy_target_powers(ah, chan,
1393 ath9k_hw_get_legacy_target_powers(ah, chan,
1397 ath9k_hw_get_target_powers(ah, chan,
1404 ath9k_hw_get_target_powers(ah, chan,
1408 ath9k_hw_get_legacy_target_powers(ah, chan,
1578 ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1586 struct ath_hal_5416 *ahp = AH5416(ah);
1617 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1626 if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
1628 (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
1637 ath9k_hw_get_legacy_target_powers(ah, chan,
1641 ath9k_hw_get_legacy_target_powers(ah, chan,
1645 ath9k_hw_get_target_powers(ah, chan,
1652 ath9k_hw_get_target_powers(ah, chan,
1656 ath9k_hw_get_legacy_target_powers(ah, chan,
1660 ath9k_hw_get_legacy_target_powers(ah, chan,
1815 ath9k_hw_def_set_txpower(struct ath_hal *ah, struct ath9k_channel *chan,
1819 struct ath_hal_5416 *ahp = AH5416(ah);
1835 if (!ath9k_hw_set_def_power_per_rate_table(ah, chan,
1848 if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) {
1860 if (AR_SREV_9280_10_OR_LATER(ah)) {
1865 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1870 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1877 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1882 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1889 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1894 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1901 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1910 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1920 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1927 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1938 if (AR_SREV_9280_10_OR_LATER(ah))
1939 ah->ah_maxPowerLevel =
1942 ah->ah_maxPowerLevel = ratesArray[i];
1948 ath9k_hw_4k_set_txpower(struct ath_hal *ah,
1955 struct ath_hal_5416 *ahp = AH5416(ah);
1970 if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan,
1981 if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) {
1993 if (AR_SREV_9280_10_OR_LATER(ah)) {
1998 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
2003 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
2010 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
2015 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
2022 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
2027 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
2034 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
2044 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
2054 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
2068 if (AR_SREV_9280_10_OR_LATER(ah))
2069 ah->ah_maxPowerLevel =
2072 ah->ah_maxPowerLevel = ratesArray[i];
2078 ath9k_hw_set_txpower(struct ath_hal *ah,
2085 struct ath_hal_5416 *ahp = AH5416(ah);
2089 val = ath9k_hw_def_set_txpower(ah, chan, cfgCtl,
2093 val = ath9k_hw_4k_set_txpower(ah, chan, cfgCtl,
2100 ath9k_hw_set_def_addac(struct ath_hal *ah, struct ath9k_channel *chan)
2104 struct ath_hal_5416 *ahp = AH5416(ah);
2108 if (ah->ah_macVersion != AR_SREV_VERSION_9160)
2122 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
2161 ath9k_hw_set_4k_addac(struct ath_hal *ah, struct ath9k_channel *chan)
2164 struct ath_hal_5416 *ahp = AH5416(ah);
2168 if (ah->ah_macVersion != AR_SREV_VERSION_9160)
2185 ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan)
2187 struct ath_hal_5416 *ahp = AH5416(ah);
2190 ath9k_hw_set_def_addac(ah, chan);
2192 ath9k_hw_set_4k_addac(ah, chan);
2197 ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah,
2201 struct ath_hal_5416 *ahp = AH5416(ah);
2211 (void) ath9k_hw_get_eeprom_antenna_cfg(ah, chan, 0, &ant_config);
2212 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2215 if (AR_SREV_9280(ah)) {
2220 if (AR_SREV_5416_V20_OR_LATER(ah) &&
2227 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
2230 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
2231 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
2239 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
2244 if (AR_SREV_9280_10_OR_LATER(ah)) {
2245 REG_RMW_FIELD(ah,
2251 REG_RMW_FIELD(ah,
2257 REG_RMW_FIELD(ah,
2263 REG_RMW_FIELD(ah,
2270 REG_WRITE(ah,
2273 (REG_READ(ah,
2280 REG_WRITE(ah,
2283 (REG_READ(ah,
2291 if (AR_SREV_9280_10_OR_LATER(ah)) {
2292 REG_RMW_FIELD(ah,
2297 REG_RMW_FIELD(ah,
2303 REG_WRITE(ah,
2305 (REG_READ(ah,
2311 REG_WRITE(ah,
2314 (REG_READ(ah,
2324 if (AR_SREV_9280_10_OR_LATER(ah)) {
2326 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
2330 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
2334 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
2338 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
2343 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
2347 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
2351 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
2355 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
2360 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
2364 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
2372 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
2376 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
2378 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
2381 if (!AR_SREV_9280_10_OR_LATER(ah))
2382 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2386 REG_WRITE(ah, AR_PHY_RF_CTL4,
2392 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
2394 if (AR_SREV_9280_10_OR_LATER(ah)) {
2395 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
2397 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
2401 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
2403 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
2410 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
2413 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
2420 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
2429 ath9k_hw_eeprom_set_4k_board_values(struct ath_hal *ah,
2433 struct ath_hal_5416 *ahp = AH5416(ah);
2447 (void) ath9k_hw_get_eeprom_antenna_cfg(ah, chan, 0, &ant_config);
2448 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2451 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
2454 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
2455 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
2464 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2466 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2468 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2471 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2475 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
2477 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
2480 if (AR_SREV_9285_11(ah))
2481 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
2487 regVal = REG_READ(ah, 0x99ac);
2494 REG_WRITE(ah, 0x99ac, regVal);
2495 regVal = REG_READ(ah, 0x99ac);
2496 regVal = REG_READ(ah, 0xa208);
2499 REG_WRITE(ah, 0xa208, regVal);
2500 regVal = REG_READ(ah, 0xa208);
2543 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2545 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2547 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2549 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2551 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2554 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2556 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2558 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2560 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2562 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2565 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2567 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2569 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2571 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2573 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2577 if (AR_SREV_9285_11(ah))
2578 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
2580 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
2582 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
2585 REG_WRITE(ah, AR_PHY_RF_CTL4,
2591 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
2593 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
2595 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
2600 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
2602 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
2609 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
2617 ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, struct ath9k_channel *chan)
2619 struct ath_hal_5416 *ahp = AH5416(ah);
2623 val = ath9k_hw_eeprom_set_def_board_values(ah, chan);
2625 val = ath9k_hw_eeprom_set_4k_board_values(ah, chan);
2631 ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hal *ah,
2635 struct ath_hal_5416 *ahp = AH5416(ah);
2664 ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hal *ah,
2668 struct ath_hal_5416 *ahp = AH5416(ah);
2684 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
2688 struct ath_hal_5416 *ahp = AH5416(ah);
2692 val = ath9k_hw_get_def_eeprom_antenna_cfg(ah, chan,
2695 val = ath9k_hw_get_4k_eeprom_antenna_cfg(ah, chan,
2703 ath9k_hw_get_4k_num_ant_config(struct ath_hal *ah,
2710 ath9k_hw_get_def_num_ant_config(struct ath_hal *ah,
2713 struct ath_hal_5416 *ahp = AH5416(ah);
2731 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
2734 struct ath_hal_5416 *ahp = AH5416(ah);
2738 val = ath9k_hw_get_def_num_ant_config(ah, freq_band);
2740 val = ath9k_hw_get_4k_num_ant_config(ah, freq_band);
2746 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, uint16_t i, boolean_t is2GHz)
2753 struct ath_hal_5416 *ahp = AH5416(ah);
2758 i, is2GHz, ah->ah_config.spurchans[i][is2GHz]));
2760 switch (ah->ah_config.spurmode) {
2764 spur_val = ah->ah_config.spurchans[i][is2GHz];
2783 ath9k_hw_get_eeprom_4k(struct ath_hal *ah,
2786 struct ath_hal_5416 *ahp = AH5416(ah);
2829 ath9k_hw_get_eeprom_def(struct ath_hal *ah, enum eeprom_param param)
2831 struct ath_hal_5416 *ahp = AH5416(ah);
2903 ath9k_hw_get_eeprom(struct ath_hal *ah, enum eeprom_param param)
2905 struct ath_hal_5416 *ahp = AH5416(ah);
2909 val = ath9k_hw_get_eeprom_def(ah, param);
2911 val = ath9k_hw_get_eeprom_4k(ah, param);
2917 ath9k_hw_eeprom_attach(struct ath_hal *ah)
2920 struct ath_hal_5416 *ahp = AH5416(ah);
2922 if (ath9k_hw_use_flash(ah))
2923 (void) ath9k_hw_flash_map(ah);
2925 if (AR_SREV_9285(ah))
2930 if (!ath9k_hw_fill_eeprom(ah))
2933 status = ath9k_hw_check_eeprom(ah);