Lines Matching refs:ah
40 ath9k_hw_nf_in_range(struct ath_hal *ah, signed short nf)
106 ath9k_hw_do_getnf(struct ath_hal *ah,
111 if (AR_SREV_9280_10_OR_LATER(ah))
112 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
114 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
122 if (AR_SREV_9280_10_OR_LATER(ah))
123 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
126 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
135 if (!AR_SREV_9280(ah)) {
136 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
145 if (AR_SREV_9280_10_OR_LATER(ah))
146 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
149 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
158 if (AR_SREV_9280_10_OR_LATER(ah))
159 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
162 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
171 if (!AR_SREV_9280(ah)) {
172 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
183 getNoiseFloorThresh(struct ath_hal *ah,
192 *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_5);
199 *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_2);
212 ath9k_hw_setup_calibration(struct ath_hal *ah,
215 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
221 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
227 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
232 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
237 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
244 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
249 ath9k_hw_reset_calibration(struct ath_hal *ah,
252 struct ath_hal_5416 *ahp = AH5416(ah);
255 ath9k_hw_setup_calibration(ah, currCal);
270 ath9k_hw_per_calibration(struct ath_hal *ah,
276 struct ath_hal_5416 *ahp = AH5416(ah);
281 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
284 currCal->calData->calCollect(ah);
295 currCal->calData->calPostProc(ah, numChains);
300 ath9k_hw_setup_calibration(ah, currCal);
304 ath9k_hw_reset_calibration(ah, currCal);
309 ath9k_hw_iscal_supported(struct ath_hal *ah,
313 struct ath_hal_5416 *ahp = AH5416(ah);
333 ath9k_hw_iqcal_collect(struct ath_hal *ah)
335 struct ath_hal_5416 *ahp = AH5416(ah);
340 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
342 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
344 (int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
354 ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
356 struct ath_hal_5416 *ahp = AH5416(ah);
361 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
363 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
365 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
367 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
380 ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
382 struct ath_hal_5416 *ahp = AH5416(ah);
387 (int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
389 (int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
391 (int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
393 (int32_t)REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
406 ath9k_hw_iqcalibrate(struct ath_hal *ah, uint8_t numChains)
408 struct ath_hal_5416 *ahp = AH5416(ah);
469 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
472 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
482 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
487 ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, uint8_t numChains)
489 struct ath_hal_5416 *ahp = AH5416(ah);
531 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
534 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
541 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
542 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
547 ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, uint8_t numChains)
549 struct ath_hal_5416 *ahp = AH5416(ah);
591 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
594 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
600 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
601 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
606 ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
609 struct ath_hal_5416 *ahp = AH5416(ah);
611 ath9k_regd_check_channel(ah, chan);
616 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
638 if (!ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType))
652 ath9k_hw_start_nfcal(struct ath_hal *ah)
654 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
656 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
658 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
663 ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
678 if (AR_SREV_9280(ah))
686 h = ah->nfCalHist;
691 val = REG_READ(ah, ar5416_cca_regs[i]);
694 REG_WRITE(ah, ar5416_cca_regs[i], val);
698 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
700 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
702 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
705 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
713 val = REG_READ(ah, ar5416_cca_regs[i]);
716 REG_WRITE(ah, ar5416_cca_regs[i], val);
722 ath9k_hw_getnf(struct ath_hal *ah, struct ath9k_channel *chan)
729 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
737 ath9k_hw_do_getnf(ah, nfarray);
739 if (getNoiseFloorThresh(ah, chan, &nfThresh) &&
752 h = ah->nfCalHist;
762 ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
767 if (AR_SREV_9280(ah))
769 else if (AR_SREV_9285(ah))
775 ah->nfCalHist[i].currIndex = 0;
776 ah->nfCalHist[i].privNF = noise_floor;
777 ah->nfCalHist[i].invalidNFcount =
780 ah->nfCalHist[i].nfCalBuffer[j] = noise_floor;
786 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
791 ichan = ath9k_regd_check_channel(ah, chan);
799 enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan);
804 if (!ath9k_hw_nf_in_range(ah, nf))
811 ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
815 struct ath_hal_5416 *ahp = AH5416(ah);
817 struct ath9k_channel *ichan = ath9k_regd_check_channel(ah, chan);
831 ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
838 ath9k_hw_reset_calibration(ah, currCal);
844 (void) ath9k_hw_getnf(ah, ichan);
845 ath9k_hw_loadnf(ah, ah->ah_curchan);
846 ath9k_hw_start_nfcal(ah);
859 ath9k_hw_9285_pa_cal(struct ath_hal *ah)
875 if (AR_SREV_9285_11(ah)) {
876 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
881 regList[i][1] = REG_READ(ah, regList[i][0]);
883 regVal = REG_READ(ah, 0x7834);
885 REG_WRITE(ah, 0x7834, regVal);
886 regVal = REG_READ(ah, 0x9808);
888 REG_WRITE(ah, 0x9808, regVal);
890 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
891 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
892 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
893 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
894 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
895 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
896 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
897 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 1);
898 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
899 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
900 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
901 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
902 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
903 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 7);
905 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
907 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
908 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
911 regVal = REG_READ(ah, 0x7834);
913 REG_WRITE(ah, 0x7834, regVal);
915 regVal = REG_READ(ah, 0x7834);
917 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
919 REG_WRITE(ah, 0x7834, regVal);
922 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
924 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
925 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
926 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
927 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
934 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
935 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
937 regVal = REG_READ(ah, 0x7834);
939 REG_WRITE(ah, 0x7834, regVal);
940 regVal = REG_READ(ah, 0x9808);
942 REG_WRITE(ah, 0x9808, regVal);
945 REG_WRITE(ah, regList[i][0], regList[i][1]);
947 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
949 if (AR_SREV_9285_11(ah))
950 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
955 ath9k_hw_init_cal(struct ath_hal *ah,
958 struct ath_hal_5416 *ahp = AH5416(ah);
959 struct ath9k_channel *ichan = ath9k_regd_check_channel(ah, chan);
961 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
962 REG_READ(ah, AR_PHY_AGC_CONTROL) |
965 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
972 if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))
973 ath9k_hw_9285_pa_cal(ah);
975 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
976 REG_READ(ah, AR_PHY_AGC_CONTROL) |
981 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
982 if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
991 if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
1000 if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
1013 ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr);