Lines Matching refs:ah
28 ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, struct ath9k_channel *chan)
30 struct ath_hal_5416 *ahp = AH5416(ah);
50 ath9k_hw_ani_control(struct ath_hal *ah, enum ath9k_ani_cmd cmd, int param)
52 struct ath_hal_5416 *ahp = AH5416(ah);
61 "ah->ah_sc, ATH_DBG_ANI",
69 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
72 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
75 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
78 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
98 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
101 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
104 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
107 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
110 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
113 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
117 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
120 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
123 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
126 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
131 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
134 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
150 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
175 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
197 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
235 ath9k_hw_update_mibstats(struct ath_hal *ah, struct ath9k_mib_stats *stats)
237 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
238 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
239 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
240 stats->rts_good += REG_READ(ah, AR_RTS_OK);
241 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
245 ath9k_ani_restart(struct ath_hal *ah)
247 struct ath_hal_5416 *ahp = AH5416(ah);
250 if (!DO_ANI(ah))
279 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
280 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
281 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
282 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
284 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
291 ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
293 struct ath_hal_5416 *ahp = AH5416(ah);
294 struct ath9k_channel *chan = ah->ah_curchan;
299 if (!DO_ANI(ah))
305 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
312 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
318 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
320 (void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
328 if (ath9k_hw_ani_control(ah,
331 (void) ath9k_hw_ani_control(ah,
337 (void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
343 (void) ath9k_hw_ani_control(ah,
347 (void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
351 mode = ath9k_hw_chan2wmode(ah, chan);
354 (void) ath9k_hw_ani_control(ah,
358 (void) ath9k_hw_ani_control(ah,
366 ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
368 struct ath_hal_5416 *ahp = AH5416(ah);
369 struct ath9k_channel *chan = ah->ah_curchan;
374 if (!DO_ANI(ah))
379 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
384 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
386 (void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
394 (void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
397 mode = ath9k_hw_chan2wmode(ah, chan);
400 (void) ath9k_hw_ani_control(ah,
407 ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
409 struct ath_hal_5416 *ahp = AH5416(ah);
415 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
417 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
428 if (ath9k_hw_ani_control(ah,
434 if (ath9k_hw_ani_control(ah,
441 if (ath9k_hw_ani_control(ah,
450 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
456 (void) ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
463 ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
465 struct ath_hal_5416 *ahp = AH5416(ah);
470 txFrameCount = REG_READ(ah, AR_TFCNT);
471 rxFrameCount = REG_READ(ah, AR_RFCNT);
472 cycleCount = REG_READ(ah, AR_CCCNT);
493 ath9k_ani_reset(struct ath_hal *ah)
495 struct ath_hal_5416 *ahp = AH5416(ah);
497 struct ath9k_channel *chan = ah->ah_curchan;
503 if (!DO_ANI(ah))
506 index = ath9k_hw_get_ani_channel_idx(ah, chan);
510 if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA &&
511 ah->ah_opmode != ATH9K_M_IBSS) {
513 "Reset ANI state opmode %u\n", ah->ah_opmode));
516 (void) ath9k_hw_ani_control(ah,
518 (void) ath9k_hw_ani_control(ah,
520 (void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
522 (ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
524 (void) ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
527 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
530 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
532 ah->ah_config.ofdm_trig_high;
534 ah->ah_config.ofdm_trig_low;
536 ah->ah_config.cck_trig_high;
538 ah->ah_config.cck_trig_low;
540 ath9k_ani_restart(ah);
545 (void) ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
548 (void) ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
552 (ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
555 (void) ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
558 (void) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
561 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
563 ath9k_ani_restart(ah);
564 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
565 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
568 ath9k_ani_restart(ah);
569 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
576 ath9k_hw_ani_monitor(struct ath_hal *ah, const struct ath9k_node_stats *stats,
579 struct ath_hal_5416 *ahp = AH5416(ah);
586 listenTime = ath9k_hw_ani_get_listen_time(ah);
589 ath9k_ani_restart(ah);
599 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
601 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
602 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
612 REG_WRITE(ah, AR_PHY_ERR_1,
614 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
623 REG_WRITE(ah, AR_PHY_ERR_2,
625 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
642 if (!DO_ANI(ah))
650 ath9k_hw_ani_lower_immunity(ah);
651 ath9k_ani_restart(ah);
655 ath9k_hw_ani_ofdm_err_trigger(ah);
656 ath9k_ani_restart(ah);
659 ath9k_hw_ani_cck_err_trigger(ah);
660 ath9k_ani_restart(ah);
666 ath9k_hw_phycounters(struct ath_hal *ah)
668 struct ath_hal_5416 *ahp = AH5416(ah);
674 ath9k_enable_mib_counters(struct ath_hal *ah)
676 struct ath_hal_5416 *ahp = AH5416(ah);
681 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
683 REG_WRITE(ah, AR_FILT_OFDM, 0);
684 REG_WRITE(ah, AR_FILT_CCK, 0);
685 REG_WRITE(ah, AR_MIBC,
687 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
688 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
692 ath9k_hw_disable_mib_counters(struct ath_hal *ah)
694 struct ath_hal_5416 *ahp = AH5416(ah);
700 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
702 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
704 REG_WRITE(ah, AR_FILT_OFDM, 0);
705 REG_WRITE(ah, AR_FILT_CCK, 0);
709 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, uint32_t *rxc_pcnt,
715 uint32_t rc = REG_READ(ah, AR_RCCNT);
716 uint32_t rf = REG_READ(ah, AR_RFCNT);
717 uint32_t tf = REG_READ(ah, AR_TFCNT);
718 uint32_t cc = REG_READ(ah, AR_CCCNT);
754 ath9k_hw_procmibevent(struct ath_hal *ah,
757 struct ath_hal_5416 *ahp = AH5416(ah);
761 REG_WRITE(ah, AR_FILT_OFDM, 0);
762 REG_WRITE(ah, AR_FILT_CCK, 0);
763 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
764 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
767 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
770 if (!DO_ANI(ah))
774 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
775 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
799 ath9k_hw_ani_ofdm_err_trigger(ah);
801 ath9k_hw_ani_cck_err_trigger(ah);
803 ath9k_ani_restart(ah);
808 ath9k_hw_ani_setup(struct ath_hal *ah)
810 struct ath_hal_5416 *ahp = AH5416(ah);
827 ath9k_hw_ani_attach(struct ath_hal *ah)
829 struct ath_hal_5416 *ahp = AH5416(ah);
869 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
870 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
871 ath9k_enable_mib_counters(ah);
874 if (ah->ah_config.enable_ani)
879 ath9k_hw_ani_detach(struct ath_hal *ah)
881 struct ath_hal_5416 *ahp = AH5416(ah);
887 ath9k_hw_disable_mib_counters(ah);
888 REG_WRITE(ah, AR_PHY_ERR_1, 0);
889 REG_WRITE(ah, AR_PHY_ERR_2, 0);