Cross Reference: /illumos-gate/usr/src/uts/common/io/1394/adapters/hci1394

Lines Matching defs:csr_handle
103     hci1394_csr_handle_t *csr_handle)
110 	ASSERT(csr_handle != NULL);
117 	*csr_handle = csr;
135 hci1394_csr_fini(hci1394_csr_handle_t *csr_handle)
140 	ASSERT(csr_handle != NULL);
143 	csr = (hci1394_csr_t *)*csr_handle;
146 	*csr_handle = NULL;
157 hci1394_csr_resume(hci1394_csr_handle_t csr_handle)
159 	ASSERT(csr_handle != NULL);
161 	hci1394_csr_state_init(csr_handle);
171 hci1394_csr_node_capabilities(hci1394_csr_handle_t csr_handle,
174 	ASSERT(csr_handle != NULL);
179 	mutex_enter(&csr_handle->csr_mutex);
180 	*capabilities = csr_handle->csr_capabilities;
181 	mutex_exit(&csr_handle->csr_mutex);
195 hci1394_csr_state_get(hci1394_csr_handle_t csr_handle, uint32_t *state)
197 	ASSERT(csr_handle != NULL);
202 	mutex_enter(&csr_handle->csr_mutex);
203 	*state = csr_handle->csr_state;
204 	mutex_exit(&csr_handle->csr_mutex);
219 hci1394_csr_state_bset(hci1394_csr_handle_t csr_handle, uint32_t state)
224 	ASSERT(csr_handle != NULL);
228 	mutex_enter(&csr_handle->csr_mutex);
239 	    (hci1394_ohci_root_check(csr_handle->csr_ohci))) {
240 		hci1394_ohci_cycle_master_enable(csr_handle->csr_ohci);
244 	csr_handle->csr_state |= supported_state;
246 	mutex_exit(&csr_handle->csr_mutex);
261 hci1394_csr_state_bclr(hci1394_csr_handle_t csr_handle, uint32_t state)
266 	ASSERT(csr_handle != NULL);
270 	mutex_enter(&csr_handle->csr_mutex);
281 	    (hci1394_ohci_root_check(csr_handle->csr_ohci))) {
282 		hci1394_ohci_cycle_master_disable(csr_handle->csr_ohci);
286 	csr_handle->csr_state &= ~state;
288 	mutex_exit(&csr_handle->csr_mutex);
300 hci1394_csr_split_timeout_hi_get(hci1394_csr_handle_t csr_handle,
303 	ASSERT(csr_handle != NULL);
308 	mutex_enter(&csr_handle->csr_mutex);
309 	*split_timeout_hi = csr_handle->csr_split_timeout_hi;
310 	mutex_exit(&csr_handle->csr_mutex);
323 hci1394_csr_split_timeout_lo_get(hci1394_csr_handle_t csr_handle,
326 	ASSERT(csr_handle != NULL);
331 	mutex_enter(&csr_handle->csr_mutex);
337 	*split_timeout_lo = csr_handle->csr_split_timeout_lo <<
340 	mutex_exit(&csr_handle->csr_mutex);
357 hci1394_csr_split_timeout_hi_set(hci1394_csr_handle_t csr_handle,
360 	ASSERT(csr_handle != NULL);
364 	mutex_enter(&csr_handle->csr_mutex);
370 	csr_handle->csr_split_timeout_hi = split_timeout_hi &
372 	csr_handle->csr_split_timeout = CSR_SPLIT_TIMEOUT(
373 	    csr_handle->csr_split_timeout_hi, csr_handle->csr_split_timeout_lo);
375 	mutex_exit(&csr_handle->csr_mutex);
391 hci1394_csr_split_timeout_lo_set(hci1394_csr_handle_t csr_handle,
394 	ASSERT(csr_handle != NULL);
398 	mutex_enter(&csr_handle->csr_mutex);
405 	csr_handle->csr_split_timeout_lo = split_timeout_lo >>
409 	if (csr_handle->csr_split_timeout_lo < CSR_MIN_SPLIT_TIMEOUT_LO) {
410 		csr_handle->csr_split_timeout_lo = CSR_MIN_SPLIT_TIMEOUT_LO;
411 	} else if (csr_handle->csr_split_timeout_lo >
413 		csr_handle->csr_split_timeout_lo = CSR_MAX_SPLIT_TIMEOUT_LO;
417 	csr_handle->csr_split_timeout = CSR_SPLIT_TIMEOUT(
418 	    csr_handle->csr_split_timeout_hi, csr_handle->csr_split_timeout_lo);
420 	mutex_exit(&csr_handle->csr_mutex);
434 hci1394_csr_split_timeout_get(hci1394_csr_handle_t csr_handle)
439 	ASSERT(csr_handle != NULL);
443 	mutex_enter(&csr_handle->csr_mutex);
446 	split_timeout = csr_handle->csr_split_timeout;
448 	mutex_exit(&csr_handle->csr_mutex);
466 hci1394_csr_bus_reset(hci1394_csr_handle_t csr_handle)
468 	ASSERT(csr_handle != NULL);
472 	mutex_enter(&csr_handle->csr_mutex);
475 	csr_handle->csr_state &= ~IEEE1394_CSR_STATE_ABDICATE;
478 	if (hci1394_ohci_root_check(csr_handle->csr_ohci) == B_FALSE) {
483 		csr_handle->csr_was_root = B_FALSE;
490 		csr_handle->csr_state &= ~IEEE1394_CSR_STATE_CMSTR;
496 	} else if (csr_handle->csr_was_root == B_FALSE) {
499 		csr_handle->csr_was_root = B_TRUE;
506 		if (hci1394_ohci_cmc_check(csr_handle->csr_ohci)) {
507 			csr_handle->csr_state |= IEEE1394_CSR_STATE_CMSTR;
508 			hci1394_ohci_cycle_master_enable(csr_handle->csr_ohci);
516 			csr_handle->csr_state &= ~IEEE1394_CSR_STATE_CMSTR;
517 			hci1394_ohci_cycle_master_disable(csr_handle->csr_ohci);
526 	mutex_exit(&csr_handle->csr_mutex);