Cross Reference: /illumos-gate/usr/src/lib/libdisasm/common/dis_sparc

Lines Matching refs:rs1
166 	uint32_t rs1:5;
172 	uint32_t rs1:5;
189 	uint32_t rs1:5;
199 	uint32_t rs1:5;
213 	uint32_t rs1:5;
221 	uint32_t rs1:5;
235 	uint32_t rs1:5;
247 	uint32_t rs1:5;
287 	uint32_t rs1:5;
297 	uint32_t rs1:5;
311 	uint32_t rs1:5;
319 	uint32_t rs1:5;
334 	uint32_t rs1:5;
346 	uint32_t rs1:5;
362 	uint32_t rs1:5;
374 	uint32_t rs1:5;
389 	uint32_t rs1:5;
401 	uint32_t rs1:5;
416 	uint32_t rs1:5;
424 	uint32_t rs1:5;
465 	uint32_t rs1:5;
475 	uint32_t rs1:5;
813 			prt_field("rs1", f->f2c.rs1, 5);
847 		r = get_regname(dhp, FLG_RS1_VAL(flags), f->f2c.rs1);
906  * format: casa/casxa [%rs1] imm_asi, %rs2, %rd
907  *	    casa/casxa [%rs1] %asi, %rs2, %rd
912  * casa  [%rs1]#ASI_P, %rs2, %rd    -> cas   [%rs1], %rs2, %rd
913  * casa  [%rs1]#ASI_P_L, %rs2, %rd  -> casl  [%rs1], %rs2, %rd
914  * casxa [%rs1]#ASI_P, %rs2, %rd    -> casx  [%rs1], %rs2, %rd
915  * casxa [%rs1]#ASI_P_L, %rs2, %rd  -> casxl [%rs1], %rs2, %rd
955 	bprintf(dhp, "[%s]", reg_names[f->f3.rs1]);
972  * format: ldXX [%rs1 + %rs2], %rd	  load, i==0
973  *	    ldXX [%rs1 +/- nn], %rd	  load, i==1
974  *	    ldXX [%rs1 + %rs2] #XX, %rd   load w/ imm_asi, i==0
975  *	    ldXX [%rs1 +/- nn] %asi, %rd  load from asi[%asi], i==1
977  *	    stXX %rd, [%rs1 + %rs2]	  store, i==0
978  *	    stXX %rd, [%rs1 +/- nn]	  store, i==1
979  *	    stXX %rd, [%rs1 + %rs1] #XX   store to imm_asi, i==0
980  *	    stXX %rd, [%rs1 +/-nn] %asi   store to asi[%asi], i==1
986  * When %rs1, %rs2 or nn are 0, they are not printed, i.e.
987  * [ %rs1 + 0x0 ], %rd -> [%rs1], %rd for example
1016 		prt_field("rs1", f->f3.rs1, 5);
1196 				    get_regname(dhp, REG_FPD, f->f3.rs1));
1258 		prt_field("rs1", f->fcp.rs1, 5);
1287 	int ridx = f->f3.rs1;
1303 		if ((f->f3.rd == 0) && (f->f3.rs1 == 15) && (f->f3.i == 0)) {
1309 		if ((v9 != 0) && (f->f3.rd == 0) && (f->f3.rs1 == 15) &&
1392 		if (v9 != 0 && f->f3.rd == 15 && f->f3.rs1 == 0 &&
1406 			if (f->f3.rs1 == 0) {
1466 			bprintf(dhp, "%s, ", reg_names[f->f3.rs1]);
1506 	p_rs1 = ((f->ftcc.rs1 != 0) ||
1515 		    (p_rs1 != 0) ? reg_names[f->ftcc2.rs1] : "",
1522 		    (p_rs1 != 0) ? reg_names[f->ftcc2.rs1] : "",
1553 		    reg_names[f->f3.rs1], cnt, reg_names[f->f3.rd]);
1555 		bprintf(dhp, "%s, %s, %s", reg_names[f->f3.rs1],
1574 			if (f->f3.rs1 == 15) {
1579 			if (f->f3.rs1 == 31) {
1615 		prt_field("rs1", f->f3.rs1, 5);
1638 		if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1645 		if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1661 			if (f->f3.rs1 == f->f3.rd) {
1670 		    (f->f3.rs1 == 0)) {
1676 		if (f->f3.rs1 == 0) {
1690 		if (f->f3.rs1 == 0 && f->f3.i == 0 && f->f3.rs2 == f->f3.rd) {
1696 		if (f->f3.rs1 == 0 && f->f3.i == 0 && f->f3.rs2 != f->f3.rd) {
1705 		if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1712 		if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1729 		 *	 xnor %rs1, 0x0 or %g0, %rd
1737 		if (f->f3.rs1 == f->f3.rd)
1752 		if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1759 		if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1783 		f->f3.rd = f->f3.rs1;
1793 		if (f->f3.rs1 == 0 && f->f3.rd == 0 && f->f3.i == 0) {
1823 		if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1830 		if (f->f3.rs1 == f->f3.rd && f->f3.i == 1 &&
1884 		if (f->f3.rs1 != 0 || f->f3.rs2 != 0 || f->f3.rd != 0)
1983 	bprintf(dhp, "%s, ", reg_names[f->f3d.rs1]);
2010 		prt_field("rs1", f->f3.rs1, 5);
2063 			prt_field("rs1", f->f3.rs1, 5);
2077 			prt_field("rs1", f->f3.rs1, 5);
2132 			prt_field("rs1", f->f3.rs1, 5);
2160 	    get_regname(dhp, FLG_P1_VAL(flags), f->fused.rs1),
2376 		p1 |= ((f->f3a.rs1 != 0) || f->f3.rs2 == 0);
2381 		    (p1 != 0) ? reg_names[f->f3a.rs1] : "",
2391 		p1 |= (f->f3a.rs1 != 0);
2405 			    (p1 != 0) ? reg_names[f->f3a.rs1] : "",
2414 			    reg_names[f->f3a.rs1],
2424  *	 %rs1, %rs2, %rd    (i == 0)
2425  *	 %rs1, 0xnnn, %rd   (i == 1)
2446 	r1 = get_regname(dhp, FLG_P1_VAL(flags), f->f3.rs1);