Cross Reference: /illumos-gate/usr/src/grub/grub-0.97/netboot/ns8390.c

Lines Matching refs:eth_asic_base
41 static unsigned short	eth_nic_base, eth_asic_base;
120 	outb(src & 0xff, eth_asic_base + WD_GP2);
121 	outb(src >> 8, eth_asic_base + WD_GP2);
133 	outb(src & 0xff, eth_asic_base + _3COM_DALSB);
134 	outb(src >> 8, eth_asic_base + _3COM_DAMSB);
135 	outb(t503_output | _3COM_CR_START, eth_asic_base + _3COM_CR);
144 		while((inb(eth_asic_base + _3COM_STREG) & _3COM_STREG_DPRDY) == 0)
149 			*((unsigned short *)dst) = inw(eth_asic_base + ASIC_PIO);
153 			*(dst++) = inb(eth_asic_base + ASIC_PIO);
157 	outb(t503_output, eth_asic_base + _3COM_CR);
170 	outb(dst & 0xff, eth_asic_base + WD_GP2);
171 	outb(dst >> 8, eth_asic_base + WD_GP2);
184 	outb(dst & 0xff, eth_asic_base + _3COM_DALSB);
185 	outb(dst >> 8, eth_asic_base + _3COM_DAMSB);
187 	outb(t503_output | _3COM_CR_DDIR | _3COM_CR_START, eth_asic_base + _3COM_CR);
197 		while((inb(eth_asic_base + _3COM_STREG) & _3COM_STREG_DPRDY) == 0)
202 			outw(*((unsigned short *)src), eth_asic_base + ASIC_PIO);
206 			outb(*(src++), eth_asic_base + ASIC_PIO);
210 	outb(t503_output, eth_asic_base + _3COM_CR);
283 		outb(0x10, eth_asic_base + 0x06); /* disable interrupts, enable PIO */
329 	outb(t503_output, eth_asic_base + _3COM_CR);
413 		outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
419 		outb(WD_MSR_MENB, eth_asic_base + WD_MSR);
431 		outb(0, eth_asic_base + WD_MSR);
461 		outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
518 		outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
523 		outb(WD_MSR_MENB, eth_asic_base + WD_MSR);
566 		outb(0, eth_asic_base + WD_MSR);
571 		outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
636 	for (eth_asic_base = WD_LOW_BASE; eth_asic_base <= WD_HIGH_BASE;
637 		eth_asic_base += 0x20) {
640 			chksum += inb(eth_asic_base+i);
643 			inb(eth_asic_base+8) != 0xFF &&
644 			inb(eth_asic_base+9) != 0xFF)
647 	if (eth_asic_base > WD_HIGH_BASE)
651 	eth_nic_base = eth_asic_base + WD_NIC_ADDR;
655 	c = inb(eth_asic_base+WD_BID);	/* Get board id */
667 		(inb(eth_asic_base + WD_ICR) & WD_ICR_16BIT)) {
673 		 ((inb(eth_asic_base + WD_MSR) & 0x3F) << 13));
678 		unsigned int addr = inb(eth_asic_base + 0xb);
684 	outb(0x80, eth_asic_base + WD_MSR);	/* Reset */
686 		nic->node_addr[i] = inb(i+eth_asic_base+WD_LAR);
688 	printf("\n%s base %#hx", brd->name, eth_asic_base);
694 		outb(0, eth_asic_base+WD_MSR);
697 		outb(WD_MSR_MENB, eth_asic_base+WD_MSR);
698 		outb((inb(eth_asic_base+0x04) |
699 			0x80), eth_asic_base+0x04);
702 			(inb(eth_asic_base+0x0B) & 0xB0), eth_asic_base+0x0B);
703 		outb((inb(eth_asic_base+0x04) &
704 			~0x80), eth_asic_base+0x04);
708 		outb(((unsigned)(eth_bmem >> 13) & 0x3F) | 0x40, eth_asic_base+WD_MSR);
712 			eth_laar = inb(eth_asic_base + WD_LAAR);
713 			outb(WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
716 				WD_LAAR_L16EN | 1), eth_asic_base + WD_LAAR);
750 			eth_asic_base = eth_nic_base + _3COM_ASIC_OFFSET;
763 			iobase_reg = inb(eth_asic_base + _3COM_BCFR);
764 			membase_reg = inb(eth_asic_base + _3COM_PCFR);
812                 outb(_3COM_CR_RST | _3COM_CR_XSEL, eth_asic_base + _3COM_CR );
813                 outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR );
817                 outb(_3COM_CR_EALO | _3COM_CR_XSEL, eth_asic_base + _3COM_CR);
829                 outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR);
835 			_3COM_GACFR_MBS0 | _3COM_GACFR_TCM | _3COM_GACFR_NIM, eth_asic_base + _3COM_GACFR);
837                 outb(0xff, eth_asic_base + _3COM_VPTR2);
838                 outb(0xff, eth_asic_base + _3COM_VPTR1);
839                 outb(0x00, eth_asic_base + _3COM_VPTR0);
855                 outb(eth_tx_start, eth_asic_base + _3COM_PSTR);
856                 outb(eth_memsize, eth_asic_base + _3COM_PSPR);
880 			eth_asic_base = eth_nic_base + NE_ASIC_OFFSET;
884 			c = inb(eth_asic_base + NE_RESET);
885 			outb(c, eth_asic_base + NE_RESET);