Cross Reference: /illumos-gate/usr/src/grub/grub-0.97/netboot/e1000.c

Lines Matching refs:CTRL
1001 	ctrl = E1000_READ_REG(hw, CTRL);
1005 		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
1025 			E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
1033 			E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1160 	/* Set the PCI priority bit correctly in the CTRL register.  This
1165 		ctrl = E1000_READ_REG(hw, CTRL);
1166 		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1420 	ctrl = E1000_READ_REG(hw, CTRL);
1443 	 * configure the two flow control enable bits in the CTRL register.
1492 	E1000_WRITE_REG(hw, CTRL, ctrl);
1505 	   (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1550 	ctrl = E1000_READ_REG(hw, CTRL);
1558 		E1000_WRITE_REG(hw, CTRL, ctrl);
1561 		E1000_WRITE_REG(hw, CTRL, ctrl);
2070 	ctrl = E1000_READ_REG(hw, CTRL);
2115 	E1000_WRITE_REG(hw, CTRL, ctrl);
2138 	ctrl = E1000_READ_REG(hw, CTRL);
2182 	E1000_WRITE_REG(hw, CTRL, ctrl);
2420 	ctrl = E1000_READ_REG(hw, CTRL);
2545 		ctrl = E1000_READ_REG(hw, CTRL);
2547 		E1000_WRITE_REG(hw, CTRL, ctrl);
2566 		E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2680 	E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2698 	E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2727 	ctrl = E1000_READ_REG(hw, CTRL);
2741 		E1000_WRITE_REG(hw, CTRL, ctrl);
2774 	ctrl = E1000_READ_REG(hw, CTRL);
2780 	E1000_WRITE_REG(hw, CTRL, ctrl);
2793 		ctrl = E1000_READ_REG(hw, CTRL);
3018 		ctrl = E1000_READ_REG(hw, CTRL);
3019 		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3022 		E1000_WRITE_REG(hw, CTRL, ctrl);
3258 	 * To take effect CTRL.RST is required.
3517 	E1000_WRITE_REG (&hw, CTRL, E1000_CTRL_RST);