Lines Matching refs:outw

73 	outw(RX_DISABLE, BASE + VX_COMMAND);
74 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
76 outw(TX_DISABLE, BASE + VX_COMMAND);
77 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
79 outw(RX_RESET, BASE + VX_COMMAND);
81 outw(TX_RESET, BASE + VX_COMMAND);
83 outw(C_INTR_LATCH, BASE + VX_COMMAND);
84 outw(SET_RD_0_MASK, BASE + VX_COMMAND);
85 outw(SET_INTR_MASK, BASE + VX_COMMAND);
86 outw(SET_RX_FILTER, BASE + VX_COMMAND);
96 /* outw(0, BASE + VX_W0_CONFIG_CTRL); */
99 /* outw(SET_IRQ(0), BASE + VX_W0_RESOURCE_CFG); */
102 /* outw(ENABLE_DRQ_IRQ, BASE + VX_W0_CONFIG_CTRL); */
110 outw(RX_RESET, BASE + VX_COMMAND);
112 outw(TX_RESET, BASE + VX_COMMAND);
120 outw(SET_RD_0_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
122 outw(SET_INTR_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
132 outw(ACK_INTR | 0xff, BASE + VX_COMMAND);
134 outw(SET_RX_FILTER | FIL_INDIVIDUAL |
145 outw(LINKBEAT_ENABLE, BASE + VX_W4_MEDIA_TYPE);
150 outw(RX_ENABLE, BASE + VX_COMMAND);
151 outw(TX_ENABLE, BASE + VX_COMMAND);
194 outw(TX_RESET, BASE + VX_COMMAND);
195 outw(TX_ENABLE, BASE + VX_COMMAND);
205 outw(len, BASE + VX_W1_TX_PIO_WR_1);
206 outw(0x0, BASE + VX_W1_TX_PIO_WR_1); /* Second dword meaningless */
211 outw(t, BASE + VX_W1_TX_PIO_WR_1);
243 outw(ACK_INTR | cst, BASE + VX_COMMAND);
244 outw(C_INTR_LATCH, BASE + VX_COMMAND);
255 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
300 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
346 outw(EEPROM_CMD_RD | offset, BASE + VX_W0_EEPROM_COMMAND);
417 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
420 outw(0, BASE + VX_W4_MEDIA_TYPE);
426 outw(ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE);
429 outw(START_TRANSCEIVER,BASE + VX_COMMAND);
435 outw(LINKBEAT_ENABLE, BASE + VX_W4_MEDIA_TYPE);
448 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
451 outw(0, BASE + VX_W4_MEDIA_TYPE);
485 outw(GLOBAL_RESET, BASE + VX_COMMAND);
505 outw(ntohs(p[i]), BASE + VX_W2_ADDR_0 + (i * 2));