Lines Matching refs:idx
140 int idx;
150 for (idx = 0; idx < nrsrc; idx++)
151 rsrcs[idx].status = DRCTL_STATUS_ALLOW;
187 int idx;
211 for (idx = 0; idx < nrsrc; idx++) {
212 if (rsrcs[idx].status == DRCTL_STATUS_INIT)
213 rsrcs[idx].status = DRCTL_STATUS_DENY;
294 int idx;
307 for (idx = 0; idx < nrsrc; idx++) {
308 drd_dbg(" cpu[%d] = %d", idx, rsrcs[idx].res_cpu_id);
309 cpus[idx] = rsrcs[idx].res_cpu_id;
332 for (idx = 0; idx < newncpus; idx++) {
333 if (!is_cpu_in_list(newcpus[idx], cpus, ncpus))
334 oldcpus[oldncpus++] = newcpus[idx];
374 int idx;
387 for (idx = 0; idx < nrsrc; idx++) {
388 cpus[idx] = rsrcs[idx].res_cpu_id;
414 for (idx = 0; idx < oldncpus; idx++) {
415 if (!is_cpu_in_list(oldcpus[idx], cpus, ncpus))
416 newcpus[newncpus++] = oldcpus[idx];
442 for (idx = 0; idx < nrsrc; idx++) {
443 rsrcs[idx].status = DRCTL_STATUS_DENY;
469 int idx;
525 for (idx = 0; rlist[idx] != NULL; idx++) {
528 rcm_get_rsrcstate(rcm_hdl, rlist[idx], &state);
531 rsrc = cpu_rsrcstr_to_rsrc(rlist[idx], rsrcs, nrsrc);
534 drd_dbg("unable to find resource for %s", rlist[idx]);
579 int idx;
608 for (idx = 0, ridx = 0; full_rlist[idx] != NULL; idx++) {
610 rcm_get_rsrcstate(rcm_hdl, full_rlist[idx], &state);
612 rlist[ridx] = full_rlist[idx];
647 int idx;
663 for (idx = 0, cidx = 0; idx < nrsrc; idx++) {
664 if (rsrcs[idx].status != DRCTL_STATUS_CONFIG_SUCCESS)
666 drd_dbg(" cpu[%d] = %d", idx, rsrcs[idx].res_cpu_id);
667 cpus[cidx] = rsrcs[idx].res_cpu_id;
702 for (idx = 0; idx < newncpus; idx++) {
703 if (!is_cpu_in_list(newcpus[idx], cpus, cidx))
704 oldcpus[oldncpus++] = newcpus[idx];
707 for (idx = 0; idx < cidx; idx++) {
708 oldcpus[oldncpus++] = cpus[idx];
748 int idx;
765 for (idx = 0, ridx = 0; idx < nrsrc; idx++) {
768 rsrcs[idx].res_cpu_id, rsrcs[idx].status, status);
774 if (rsrcs[idx].status != status)
778 (void) sprintf(rbuf, "%s%d", RCM_CPU, rsrcs[idx].res_cpu_id);
804 int idx;
810 for (idx = 0; rlist[idx] != NULL; idx++) {
811 s_free(rlist[idx]);
851 int idx;
855 for (idx = 0; idx < nrsrc; idx++) {
856 if (rsrcs[idx].res_cpu_id == cpuid)
857 return (&rsrcs[idx]);
903 int idx;
908 for (idx = 0; idx < len; idx++) {
909 if (list[idx] == cpuid)
959 int idx;
969 for (idx = 0; idx < nrsrc; idx++) {
972 errstr = (char *)(uintptr_t)rsrcs[idx].offset;
974 drd_dbg(" cpu[%d]: cpuid=%d, status=%d, errstr='%s'", idx,
975 rsrcs[idx].res_cpu_id, rsrcs[idx].status,
983 int idx;
1005 for (idx = 0; rlist[idx] != NULL; idx++) {
1007 rcm_get_rsrcstate(rcm_hdl, rlist[idx], &state);
1008 drd_dbg(" rlist[%d]: rsrc=%s, state=%-2d (%s)", idx,
1009 rlist[idx], state, rcm_state_str[state]);
1216 int idx;
1226 for (idx = 0; idx < nrsrc; idx++) {
1229 errstr = (char *)(uintptr_t)rsrcs[idx].offset;
1232 " status=%d, errstr='%s'", idx,
1233 rsrcs[idx].res_mem_addr, rsrcs[idx].res_mem_size,
1234 rsrcs[idx].status, (errstr != NULL) ? errstr : "");
1300 int idx;
1313 for (idx = 0; idx < nrsrc; idx++)
1314 rsrcs[idx].status = DRCTL_STATUS_ALLOW;
1324 int idx;
1336 for (idx = 0; idx < nrsrc; idx++) {
1337 if (rsrcs[idx].status == DRCTL_STATUS_CONFIG_SUCCESS)
1338 change += rsrcs[idx].res_mem_size;
1339 drd_dbg(" idx=%d addr=0x%llx size=0x%llx",
1340 idx, rsrcs[idx].res_mem_addr, rsrcs[idx].res_mem_size);
1352 int idx;
1363 for (idx = 0; idx < nrsrc; idx++) {
1364 drd_dbg(" idx=%d addr=0x%llx size=0x%llx",
1365 idx, rsrcs[idx].res_mem_addr, rsrcs[idx].res_mem_size);
1366 change += rsrcs[idx].res_mem_size;
1379 for (idx = 0; idx < nrsrc; idx++) {
1380 rsrcs[idx].status = DRCTL_STATUS_DENY;
1388 for (idx = 0; idx < nrsrc; idx++)
1389 rsrcs[idx].status = DRCTL_STATUS_ALLOW;
1402 int idx;
1423 for (idx = 0; idx < nrsrc; idx++) {
1424 if (rsrcs[idx].status != DRCTL_STATUS_CONFIG_SUCCESS)
1425 change += rsrcs[idx].res_mem_size;
1426 drd_dbg(" idx=%d addr=0x%llx size=0x%llx",
1427 idx, rsrcs[idx].res_mem_addr, rsrcs[idx].res_mem_size);